參數(shù)資料
型號: DS1393U-18+
廠商: Maxim Integrated Products
文件頁數(shù): 10/26頁
文件大小: 0K
描述: IC RTC W/CHARGER 10-USOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 50
類型: 時(shí)鐘/日歷
特點(diǎn): 警報(bào)器,閏年,方波輸出,涓流充電器
時(shí)間格式: HH:MM:SS:hh(12/24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: 3 線串口
電源電壓: 1.71 V ~ 1.89 V
電壓 - 電源,電池: 1.3 V ~ 3.7 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-µMAX
包裝: 管件
DS1390–DS1394
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
18
Maxim Integrated
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit
indicates that the oscillator has stopped or was
stopped for some time and may be used to judge the
validity of the clock and calendar data. This bit is
edge-triggered and is set to logic 1 when the internal
circuitry senses the oscillator has transitioned from a
normal run state to a STOP condition. The following are
examples of conditions that can cause the OSF bit to
be set:
1) The first time power is applied.
2) The voltage present on VCC and VBACKUP is
insufficient to support oscillation.
3) The EOSC bit is turned off.
4) External influences on the crystal (i.e., noise,
leakage, etc.).
This bit remains at logic 1 until written to logic 0. This
bit can only be written to logic 0. Attempting to write
OSF to logic 1 leaves the value unchanged.
Bit 6: Alarm Flag (AF). A logic 1 in the AF bit indicates
that the time matched the alarm registers. If the AIE bit
The INTCN bit used in the DS1390/DS1393/DS1394
becomes the SQW pin-enable bit in the DS1392. This
bit powers up a zero, making SQW active.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
EOSC
0
BBSQI
RS2
RS1
ESQW
0
AIE
Control Register (0D/8Dh) (DS1392 Only)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OSF
00
0000
AF
Status Register (0E/8Eh)
is logic 1 and the INTCN bit is set to logic 1, the
SQW/INT pin is also asserted. AF is cleared when writ-
ten to logic 0. This bit can only be written to logic 0.
Attempting to write to logic 1 leaves the value
unchanged.
Trickle-Charge Register (0F/8Fh)
The simplified schematic in Figure 8 shows the basic
components of the trickle charger. The trickle-charge
select (TCS) bits (bits 4 to 7) control the selection of
the trickle charger. To prevent accidental enabling,
only a pattern on 1010 enables the trickle charger. All
other patterns disable the trickle charger. The trickle
charger is disabled when power is first applied. The
diode-select (DS) bits (bits 2 and 3) select whether or
not a diode is connected between VCC and VBACKUP.
If DS is 01, no diode is selected or if DS is 10, a diode
is selected. The ROUT bits (bits 0 and 1) select the
value of the resistor connected between VCC and
VBACKUP. Table 5 shows the resistor selected by the
resistor-select (ROUT) bits and the diode selected by
the diode-select (DS) bits.
TCS3
TCS2
TCS1
TCS0
DS1
DS0
ROUT1
ROUT0
FUNCTION
X
0
X
Disabled
X
1
X
Disabled
X
0
Disabled
101
00101
No diode, 250
resistor
101
01001
One diode, 250
resistor
101
00110
No diode, 2k
resistor
101
01010
One diode, 2k
resistor
101
00111
No diode, 4k
resistor
101
01011
One diode, 4k
resistor
000
00000
Initial default value—disabled
Table 5. Trickle-Charge Register
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