The DS1558 is in the write mode whenever WE and <" />
參數(shù)資料
型號(hào): DS1558Y-TRL
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 15/18頁(yè)
文件大?。?/td> 0K
描述: IC RTC W/NV RAM 5V 48-TQFP
標(biāo)準(zhǔn)包裝: 2,000
類型: 時(shí)鐘/日歷
特點(diǎn): 警報(bào)器,閏年,監(jiān)視計(jì)時(shí)器,Y2K
時(shí)間格式: HH:MM:SS(24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: 并聯(lián)
電源電壓: 4.5 V ~ 5.5 V
電壓 - 電源,電池: 2.5 V ~ 3.7 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
DS1558
6 of 18
DATA WRITE MODE
The DS1558 is in the write mode whenever WE and CE are in their active state. The
referenced to the latter occurring transition of
start of a write is
WE
or CE . The addresses must be hel
the cycle.
d valid throughout
CE
and WE must return inactive for a minimum of t
prior to the initiation of a subsequent
read or write cycle. Data in must be valid t
prior to the
WR
DS
end of the write and remain valid for tDH
afterward. In a typical application, the OE signal is high during a write cycle. However, OE can be active
ten
If
provided that care is taken with the data bus to avoid bus con
tion.
OE
is low prior to WE
ress inputs. A low
transitioning low, the data bus can become active with read data defined by the add
transition on WE then disables the outputs tWEZ after WE goes active.
DATA RETENTION MODE
The 5V device is fully accessible and data can be written and read only when VCC i
However, when VCC is below the power-fail point VPF (point at which write prot
internal clock registers and SRAM are blocked from any access. When V
falls below the batter
s greater than VPF.
ection occurs), the
CC
y switch
point VSO (battery supply level), device power is switched from the VCC pin to the backup battery. RTC
inal levels.
s greater than VPF.
he device power is
C t
. If VPF is greater
CC drops
VCC is returned to
All control, data, and address signals must be powered down when VCC is powered down.
558 internal clock
current is less than
g. No external protection components
are required, and none should be used. The DS1558 has two battery pins that operate independently; the
DS1558 selects the higher of the two inputs. If only one battery is used, the battery should be attached to
VBAT1, and VBAT2 should be grounded.
INTERNAL BATTERY MONITOR
The DS1558 constantly monitors the battery voltage of the internal battery. The battery-low flag (BLF)
bit of the flags register (B4 of 7FFF0h) is not writable and should always be a 0 when read. If a 1 is ever
present, both battery inputs are below 1.8V and both the contents of the RTC and RAM are questionable.
POWER-ON RESET
A temperature-compensated comparator circuit monitors the level of VCC. When VCC falls to the power-
fail trip point, the
operation and SRAM data are maintained from the battery until VCC is returned to nom
The 3.3V device is fully accessible and data can be written and read only when VCC i
When VCC falls below VPF, access to the device is inhibited. If VPF is less than VSO, t
switched from VC o the internal backup lithium battery when VCC drops below VPF
than VSO, the device power is switched from VCC to the internal backup lithium battery when V
below VSO. RTC operation and SRAM data are maintained from the battery until
nominal levels.
BATTERY LONGIVITY
The battery lifetime is dependent on the RAM battery standby current and the DS1
oscillator current. The total battery current is IOSC + ICCO. When VCC is above VPF, IBAT
50nA. The DS1558 has an internal circuit to prevent battery chargin
RST
signal (open drain) is pulled low. When VCC returns to nominal levels, the RST
signal continues to be pulled low for a period of 40ms to 200ms. The power-on reset function is
independent of the RTC oscillator and thus is operational whether or not the oscillator is enabled.
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