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| 型號： | DS1642-70+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RAM TIMEKEEP NV 70NS 24-EDIP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 14 |
| 類型： | 時鐘/日歷 |
| 特點： | 閏年，NVSRAM |
| 存儲容量： | 2KB |
| 時間格式： | HH:MM:SS（24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | 并聯(lián) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP 模塊（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 24-EDIP |
| 包裝： | 管件 |
DS1642
3 of 13
CLOCK OPERATIONS–READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1642 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, the 7th most significant bit in the control register.
As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the
count, that is day, date, and time that was current at the moment the halt command was issued. However,
the internal clock registers of the double-buffered system continue to update so that the clock accuracy is
not affected by the access of data. All of the DS1642 registers are updated simultaneously after the clock
status is reset. Updating occurs within a second after the read bit is written to 0.
Figure 1. DS1642 BLOCK DIAGRAM
Table 1. TRUTH TABLE
VCC
CE
OE
WE
MODE
DQ
POWER
VIH
X
Deselect
High-Z
Standby
VIL
X
VIL
Write
Data In
Active
VIL
VIH
Read
Data Out
Active
5V ±10%
VIL
VIH
Read
High-Z
Active
<4.5V > VBAT
X
Deselect
High-Z
CMOS Standby
<VBAT
X
Deselect
High-Z
Data Retention Mode
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