參數(shù)資料
型號(hào)： DS1643-100
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 13/17頁(yè)
文件大?。?/td> 0K
描述： IC RAM TIMEKEEP NV 100NS 28-EDIP
標(biāo)準(zhǔn)包裝： 12
類型： 時(shí)鐘/日歷
特點(diǎn)： 閏年，NVSRAM
存儲(chǔ)容量： 8KB
時(shí)間格式： HH:MM:SS（24 小時(shí)）
數(shù)據(jù)格式： YY-MM-DD-dd
接口： 并聯(lián)
電源電壓： 4.5 V ~ 5.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 通孔
封裝/外殼： 28-DIP 模塊（0.600"，15.24mm）
供應(yīng)商設(shè)備封裝： 28-EDIP
包裝： 管件
其它名稱： DS1643100
DS1643/DS1643P
5 of 17
CLOCK ACCURACY (DIP MODULE)
The DS1643 is guaranteed to keep time accuracy to within
1 minute per month at 25C.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1643P and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module is guaranteed to keep time accuracy to within
1.53 minutes per month (35ppm) at 25C.
Table 2. Register Map—Bank1
DATA
ADDRESS
B7
B6
B5
B4
B3
B2
B1
B0
FUNCTION
RANGE
1FFF
—
Year
00-99
1FFE
X
—
Month
01-12
1FFD
X
—
Date
01-31
1FFC
X
Ft
X
—
Day
01-07
1FFB
X
—
Hour
00-23
1FFA
X
—
Minutes
00-59
1FF9
OSC
—
Seconds
00-59
1FF8
W
R
X
Control
A
OSC = STOP BIT
R = READ BIT
FT = FREQUENCY TEST
W = WRITE BIT
X = UNUSED
Note: All indicated “X” bits are not used but must be set to “0” for proper clock operation.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1643 is in the read mode whenever WE (write enable) is high and CE (chip enable) is low. The
device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid
data will be available at the DQ pins within tAA after the last address input is stable, providing that the CE
and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be
available at the latter of chip enable access (tCEA) or at output enable access time (tOEA). The state of the
data input/output pins (DQ) is controlled by CE and OE . If the outputs are activated before tAA , the data
lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE
remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1643 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or
write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active provided
that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low
the data bus can become active with read data defined by the address inputs. A low transition on WE will
then disable the outputs tWEZ after WE goes active.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS1643-100+ 功能描述:實(shí)時(shí)時(shí)鐘 NV Timekeeping RAM RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube
DS1643-12 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Real-Time Clock
DS1643-120 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Nonvolatile Timekeeping RAM
DS1643-15 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Real-Time Clock
DS1643-150 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Nonvolatile Timekeeping RAM
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