- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9392 > DS1647P-120+ (Maxim Integrated Products)IC RAM TIMEKEEP NV 120NS 34-PCM PDF資料下載
參數(shù)資料
| 型號： | DS1647P-120+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RAM TIMEKEEP NV 120NS 34-PCM |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 40 |
| 類型： | 時鐘/日歷 |
| 特點： | 閏年，NVSRAM |
| 存儲容量： | 512KB |
| 時間格式： | HH:MM:SS（24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | 并聯(lián) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電壓 - 電源，電池： | 3V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 34-PowerCap? 模塊 |
| 供應商設備封裝： | 34-PowerCap 模塊 |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1434 (CN2011-ZH PDF) |
DS1647/DS1647P
6 of 12
RETRIEVING DATA FROM RAM OR CLOCK
The DS1647 is in the read mode whenever WE (write enable) is high; CE (chip enable) is low. The
device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid
data will be available at the DQ pins within tAA after the last address input is stable, providing that the CE
and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be
available at the latter of chip-enable access (tCEA) or at output enable access time (tOEA). The state of the
data input/output pins (DQ) is controlled by CE and OE. If the outputs are activated before tAA, the data
lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE
remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1647 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring high to low transition of WE and CE. The addresses must be held valid
throughout the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of
another read or write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH
afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be
active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE
transitioning low the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the outputs tWEZ after WE goes active.
DATA-RETENTION MODE
When VCC is within nominal limits (VCC > 4.5V) the DS1647 can be accessed as described above with
read or write cycles. However, when VCC is below the power-fail point VPF (point at which write
protection occurs) the internal clock registers and RAM are blocked from all access. This is accomplished
internally by inhibiting access via the CE signal. At this time the power-fail output signal (PFO) will be
driven active low and will remain active until VCC returns to nominal levels. When VCC falls below the
level of the internal battery supply, power input is switched from the VCC pin to the internal battery and
clock activity, RAM, and clock data are maintained from the battery until VCC is returned to nominal
level.
BATTERY LONGEVITY
The DS1647 has a lithium power source that is designed to provide energy for clock activity and clock
and RAM data retention when the VCC supply is not present. The capability of this internal power supply
is sufficient to power the DS1647 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at +25°C with the internal clock oscillator running
in the absence of VCC power. Each DS1647 is shipped from Dallas Semiconductor with its lithium energy
source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than
VPF, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the
DS1647 will be longer than 10 years since no lithium battery energy is consumed when VCC is present.
相關PDF資料 |
PDF描述 |
|---|---|
| VI-J0Y-MZ | CONVERTER MOD DC/DC 3.3V 16.5W |
| VI-J0X-MZ | CONVERTER MOD DC/DC 5.2V 25W |
| VI-J0R-MZ | CONVERTER MOD DC/DC 7.5V 25W |
| VI-J0P-MZ | CONVERTER MOD DC/DC 13.8V 25W |
| M83723/75A18146 | CONN PLUG 14POS STRAIGHT W/SCKT |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS1647P-120+ | 功能描述:實時時鐘 NV Timekeeping RAM RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1648 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:TRI-STATE TTL to MOS Multiplexers/Drivers |
| DS1648J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2-Input Digital Multiplexer |
| DS1648J/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2-Input Digital Multiplexer |
| DS1649 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Hex TRI-STATEE TTL to MOS Drivers |
發(fā)布緊急采購，3分鐘左右您將得到回復。