(VCC = 0V, TA
參數(shù)資料
型號: DS1672U-33+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 11/15頁
文件大?。?/td> 0K
描述: IC TIMEKEEPER 3.3V 32-BIT 8-USOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 3,000
類型: 二進(jìn)制計數(shù)器
特點: 涓流充電器
時間格式: 二進(jìn)制
數(shù)據(jù)格式: 二進(jìn)制
接口: I²C,2 線串口
電源電壓: 2.97 V ~ 3.63 V
電壓 - 電源,電池: 1.3 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-uMAX
包裝: 帶卷 (TR)
DS1672
5 of 15
AC ELECTRICAL CHARACTERISTICS
(VCC = 0V, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock
Frequency
fSCL
Fast mode
100
400
kHz
Standard mode
100
Bus Free Time
Between a STOP and
START Condition
tBUF
Fast mode
1.3
s
Standard mode
4.7
Hold Time
(Repeated) START
Condition (Note 6)
tHD:STA
Fast mode
0.6
s
Standard mode
4.0
LOW Period of SCL
Clock
tLOW
Fast mode
1.3
s
Standard mode
4.7
HIGH Period of SCL
Clock
tHIGH
Fast mode
0.6
s
Standard mode
4.0
Setup Time for a
Repeated START
Condition
tSU:STA
Fast mode
0.6
s
Standard mode
4.7
Data Hold Time
(Notes 7, 8)
tHD:DAT
Fast mode
0
0.9
s
Standard mode
0
Data Setup Time
(Note 9)
tSU:DAT
Fast mode
100
ns
Standard mode
250
Rise Time of Both
SDA and SCL
Signals (Note 10)
tR
Fast mode
20 + 0.1CB
300
ns
Standard mode
1000
Fall Time of Both
SDA and SCL
Signals (Note 10)
tF
Fast mode
20 + 0.1CB
300
ns
Standard mode
300
Setup Time for STOP
Condition
tSU:STO
Fast mode
0.6
s
Standard mode
4.0
Capacitive Load for
Each Bus Line
(Note 10)
CB
400
pF
I/O Capacitance
CI/O
10
pF
Note 6: After this period, the first clock pulse is generated.
Note 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referenced to the VIHMIN of the SCL signal) in
order to bridge the undefined region of the falling edge of SCL.
Note 8:The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 9: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT
≥ to 250ns must then be met. This will
automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line tR max + tSU:DAT = 1000 + 250 = 1250ns before the SCL
line is released.
Note 10: CB–Total capacitance of one bus line in pF.
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