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參數(shù)資料
| 型號： | DS1678S+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 16/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC REAL TIME EVENT REC 8-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,000 |
| 類型： | 時間事件記錄器 |
| 特點： | 警報器，閏年，NVSRAM，Y2K |
| 存儲容量： | 32B |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電壓 - 電源，電池： | 2.6 V ~ 3.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
DS1678 Real-Time Event Recorder
23 of 25
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end of data to the slave
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the master to generate the STOP condition.
Figure 6 details how data transfer is accomplished on the I2C bus. Depending upon the state of the R/
W
bit, two types of data transfer are possible:
1)
Data transfer from a master tr ansmitter to a slave receiver. The first byte transmitted by the
master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge
bit after each received byte.
2)
Data transfer from a slave tr ansmitter to a master receiv er. The first byte (the slave address) is
transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last received byte, a “not acknowledge” is returned.
The master device generates all the serial clock pulses and the START and STOP conditions. A transfer is
ended with a STOP condition or with a repeated START condition. Because a repeated START condition
is also the beginning of the next serial transfer, the bus is not released.
The DS1678 can operate in the following two modes:
1)
Slave receiver mode (DS1678 w rite mode): Serial data and clock are received through SDA and
SCL. After each byte is received, the receiver transmits an acknowledge bit. START and STOP
conditions are recognized as the beginning and end of a serial transfer. The slave address byte is the
first byte received after master generates the START condition. The address byte contains the 7-bit
DS1678 address, which is 1001010, followed by the direction bit (R/
W), which is 0. The second byte
from the master is the register address. This sets the register pointer. If the write is being done to set
the register pointer, a STOP or repeated START may then be sent by the master. Otherwise, the
master then transmits each byte of data, with the DS1678 acknowledging each byte received. The
master generates a STOP condition to terminate the data write (Figure 7).
2)
Slave transmitter mode (DS1678 read mode): The first byte is received and handled as in the slave
receiver mode. However, in this mode, the direction bit indicates that the transfer direction is
reversed. Serial data is transmitted on SDA by the DS1678 while the serial clock is input on SCL. The
slave address byte is the first byte received after the master generates a START condition. The
address byte contains the 7-bit DS1678 address, which is 1001010, followed by the direction bit
(R/
W), which is 1. After receiving a valid slave address byte and direction bit, the DS1678 generates
an acknowledge on the SDA line. The DS1678 begins to transmit data on each SCL pulse starting
with the register address pointed to by the register pointer. As the master reads each byte, it must
generate an acknowledge. The DS1678 must receive a “not acknowledge” on the last byte to end a
read (Figure 7).
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