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參數(shù)資料
| 型號： | DS1689SN+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 2/36頁 |
| 文件大小： | 0K |
| 描述： | IC RTC SER NV RAM CTRL IN 28SOIC |
| 標準包裝： | 1,000 |
| 類型： | 時鐘/日歷 |
| 特點： | NVSRAM |
| 存儲容量： | 114B |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | 并聯(lián) |
| 電源電壓： | 2.7 V ~ 3.3 V，4.5 V ~ 5.5 V |
| 電壓 - 電源，電池： | 2.5 V ~ 3.7 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 28-SOIC |
| 包裝： | 帶卷 (TR) |
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DS1689/DS1693
10 of 36
The application software can select which interrupts, if any, are to be used. A total of 6 bits, including 3
bits in Register B and 3 bits in Extended Register B, enable the interrupts. The extended register locations
are described later. Writing logic 1 to an interrupt enable bit permits that interrupt to be initiated when the
event occurs. A logic 0 in the interrupt enable bit prohibits the
IRQ pin from being asserted from that
interrupt condition. If an interrupt flag is already set when an interrupt is enabled,
IRQ is immediately set
at an active level, even though the event initiating the interrupt condition may have occurred much earlier.
As a result, there are cases where the software should clear these earlier generated interrupts before first
enabling new interrupts.
When an interrupt event occurs, the relating flag bit is set to a logic 1 in Register C or in Extended
Register A. These flag bits are set regardless of the setting of the corresponding enable bit located either
in Register B or in Extended Register B. The flag bits can be used in a polling mode without enabling the
corresponding enable bits.
However, care should be taken when using the flag bits of Register C as they are automatically cleared to
0 immediately after they are read. Double latching is implemented on these bits so that bits that are set
remain stable throughout the read cycle. All bits which were set are cleared when read and new interrupts
which are pending during the read cycle are held until after the cycle is completed. One, 2, or 3 bits can
be set when reading Register C. Each utilized flag bit should be examined when read to ensure that no
interrupts are lost.
The flag bits in Extended Register A are not automatically cleared following a read. Instead, each flag bit
can be cleared to 0 only by writing 0 to that bit.
When using the flag bits with fully enabled interrupts, the
IRQ line is driven low when an interrupt flag
bit is set and its corresponding enable bit is also set.
IRQ is held low as long as at least one of the six
possible interrupt sources has it s flag and enable bits both set. The IRQF bit in Register C is 1 whenever
the
IRQ pin is being driven low as a result of one of the six possible active sources. Therefore,
determination that the DS1689/DS1693 initiated an interrupt is accomplished by reading Register C and
finding IRQF = 1. IRQF remains set until all enabled interrupt flag bits are cleared to 0.
SQUARE-WAVE OUTPUT SELECTION
The SQW pin can be programmed to output a variety of frequencies divided down from the 32.768kHz
crystal tied to X1 and X2. The square-wave output is enabled and disabled via the SQWE bit in Register
B. If the square wave is enabled (SQWE = 1), the output frequency is determined by the settings of the
E32K bit in Extended Register B and by the RS3–RS0 bits in Register A. If the E32K = 1, then a
32.768kHz square wave is output on the SQW pin regardless of the settings of RS3–RS0.
If E32K = 0, then the square-wave output frequency is determined by the RS3–RS0 bits. These bits
control a 1-of-15 decoder, which selects one of 13 taps that divide the 32.768kHz frequency. The RS3–
RS0 bits establish the SQW output frequency as shown in Table 2. In addition, RS3–RS0 bits control the
periodic interrupt selection as described below.
If SQWE1, E32K = 1, and the auxiliary battery enable bit (ABE, bank 1; register 04BH) is enabled, and
voltage is applied to VBAUX, then the 32kHz square-wave output signal is output on the SQW pin in the
absence of VCC. This facility is provided to clock external power management circuitry. If any of the
above requirements are not met, no square-wave output signal is generated on the SQW pin in the
absence of VCC.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| DS1689S-TRL | 功能描述:IC RTC SER W/NV RAM CTRL 28-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 實時時鐘 系列:- 產(chǎn)品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:時鐘/日歷 特點:警報器，閏年，SRAM 存儲容量:- 時間格式:HH:MM:SS（12/24 小時） 數(shù)據(jù)格式:YY-MM-DD-dd 接口:SPI 電源電壓:2 V ~ 5.5 V 電壓 - 電源，電池:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤 供應商設備封裝:8-TDFN EP 包裝:管件 |
| DS1691 | 功能描述:實時時鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1691 WAF | 制造商:Texas Instruments 功能描述: |
| DS1691/1692 WAF | 制造商:Texas Instruments 功能描述: |
| DS1691A | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:(RS-422/RS-423) Line Drivers with TRI-STATE Outputs |
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