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參數(shù)資料
| 型號： | DS1743WP-120IND+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 12/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC RAM Y2K 3.3V 120NS 34-PCM |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 40 |
| 類型： | 時鐘/日歷 |
| 特點： | 閏年，NVSRAM，Y2K |
| 存儲容量： | 8KB |
| 時間格式： | HH:MM:SS（24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | 并聯(lián) |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 電壓 - 電源，電池： | 3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 34-PowerCap? 模塊 |
| 供應商設備封裝： | 34-PowerCap 模塊 |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1434 (CN2011-ZH PDF) |
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
4 of 17
TIME AND DATE OPERATION
The time and date information is obtained by reading the appropriate register bytes. Table 2 shows the
RTC registers. The time and date are set or initialized by writing the appropriate register bytes. The
contents of the time and date registers are in the BCD format. The day-of-week register increments at
midnight. Values that correspond to the day of week are user-defined, but must be sequential (i.e., if 1
equals Sunday, then 2 equals Monday and so on). Illogical time and date entries result in undefined
operation.
CLOCK OPERATIONS-READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1743 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, bit 6 of the century register (see Table 2). As long
as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count that
is day, date, and time that was current at the moment the halt command was issued. However, the internal
clock registers of the double-buffered system continue to update so that the clock accuracy is not affected
by the access of data. All the DS1743 registers are updated simultaneously after the internal clock register
updating process has been re-enabled. Updating is within a second after the read bit is written to 0.
The READ bit must be a zero for a minimum of 500s to ensure the external registers are updated.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1743WP-120IND+ | 功能描述:實時時鐘 Timekeeping NV RAM RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1743WP-150 | 功能描述:實時時鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1743WP-150+ | 功能描述:實時時鐘 Timekeeping NV RAM RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1744 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Y2K-Compliant, Nonvolatile Timekeeping RAMs |
| DS1744_10 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Y2K-Compliant, Nonvolatile Timekeeping RAMs |
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