參數(shù)資料
型號: DS1747WP-C03+
廠商: Maxim Integrated Products
文件頁數(shù): 11/16頁
文件大?。?/td> 0K
描述: IC RAM NONVOL TIME KEEP 34PWRCAP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 40
類型: 時鐘/日歷
特點: 閏年,NVSRAM,Y2K
存儲容量: 512KB
時間格式: HH:MM:SS(24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: 并聯(lián)
電源電壓: 2.97 V ~ 3.63 V
電壓 - 電源,電池: 3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 34-PowerCap? 模塊
供應商設備封裝: 34-PowerCap 模塊
包裝: 管件
其它名稱: 90-1747W+PC3
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
4 of 16
Figure 1. Block Diagram
PACKAGES
The DS1747 is available in two packages (32-pin DIP and 34-pin PowerCap module). The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap
(DS9034PCX) that contains the crystal and battery. This design allows the Power-Cap to be mounted on
top of the DS1747P after the completion of the surface mount process. Mounting the PowerCap after the
surface mount process prevents damage to the crystal and battery due to the high temperatures required
for solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board
and PowerCap are ordered separately and shipped in separate containers.
TIME AND DATE OPERATIONS
The contents of the time and date registers are in BCD format. The day-of-week register increments at
midnight. Values that correspond to the day of week are user-defined, but must be sequential (i.e., if 1
equals Sunday, then 2 equals Monday and so on). Illogical time and date entries result in undefined
operation.
CLOCK OPERATIONS—READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal
updates to the DS1747 clock registers should be halted before clock data is read to prevent reading of
data in transition. However, halting the internal clock register updating process does not affect clock
accuracy. Updating is halted when a one is written into the read bit, bit 6 of the century register (see
Table 2). As long as a one remains in that position, updating is halted. After a halt is issued, the registers
reflect the count, that is day, date, and time that was current at the moment the halt command was
issued. However, the internal clock registers of the double-buffered system continue to update so that
the clock accuracy is not affected by the access of data. All the DS1747 registers are updated
simultaneously after the internal clock register updating process has been re-enabled. Updating is within
a second after the read bit is written to zero. The READ bit must be set to a zero for a minimum of
500s to ensure the external registers will be updated.
Maxim
DS1747
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