參數(shù)資料
型號: DS1805E-010+
廠商: Maxim Integrated Products
文件頁數(shù): 5/10頁
文件大?。?/td> 0K
描述: IC POT DIG ADDRESS 10K 14-TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 96
接片: 256
電阻(歐姆): 10k
電路數(shù): 1
溫度系數(shù): 標(biāo)準(zhǔn)值 550 ppm/°C
存儲器類型: 易失
接口: I²C(設(shè)備位址)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 14-TSSOP
包裝: 管件
產(chǎn)品目錄頁面: 1430 (CN2011-ZH PDF)
DS1805
Addressable Digital Potentiometer
4
_____________________________________________________________________
Note 1:
All voltages are referenced to ground.
Note 2:
ICC specified with SDA pin open. SCL = 400kHz clock rate.
Note 3:
Address inputs A0, A1, and A2 should be connected to either VCC or GND, depending on the desired address selections.
Note 4:
I/O pins of fast mode devices must not obstruct the SDA and SCL lines if VCC is switched off.
Note 5:
ISTBY specified with SDA = SCL = VCC = 5.0V.
Note 6:
Valid at +25
°C only.
Note 7:
Absolute linearity is used to determine wiper voltage versus expected voltage as determined by wiper position.
Note 8:
Relative linearity is used to determine the change in voltage between successive tap positions.
Note 9:
-3dB cutoff frequency characteristics for the DS1805 depend on potentiometer total resistance: DS1805-010, 1MHz;
DS1805-50, 200kHz; DS1805-100, 100kHz.
Note 10: A fast mode device can be used in a standard mode system, but the requirement tSU:DAT > 250ns must then be met. This
will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000ns + 250ns =
1250ns before the SCL line is released.
Note 11: After this period, the first clock pulse is generated.
Note 12: The maximum tHD:DAT has only to be met if the device does not stretch the low period (tLOW) of the SCL signal.
Note 13: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal)
in order to bridge the undefined region of the falling edge of SCL.
Note 14: CB—total capacitance of one bus line in picofarads, timing referenced to (0.9)(VCC) and (0.1)(VCC).
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.7V to 5.5V, TA = -40°C to +85°C)
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