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參數(shù)資料
| 型號(hào)： | DS1806S-050/T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DIG SEXTET 50K 20-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 接片： | 64 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 6 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 750 ppm/°C |
| 存儲(chǔ)器類型： | 易失 |
| 接口： | 3 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 帶卷 (TR) |
DS1806
4 of 8
102199
3-WIRE SERIAL PORT TIMING Figure 4
CASCADE OPERATION
A feature of the DS1806 is the ability to control multiple devices from a single processor. Multiple
DS1806s can be linked or daisy chained as shown in Figure 5. As a data bit is entered into the I/O shift
register of the DS1806, a bit will appear at the COUT terminal before a maximum delay of 50 nanoseconds.
The LSB of potentiometer-1 will always be the first out of the part at the beginning of a transaction.
Additionally, the COUT terminal is always active regardless of the state RST . However, DIN and CLK
inputs are ignored when RST is in the low state.
The COUT output of the DS1806 can be used to drive the DIN input of another DS1806. When cascading
multiple devices, the total number of bits transmitted is always 48 multiplied by the total number of
DS1806s being cascaded.
An optional feedback resistor can be placed between the COUT terminal of the last device and the first
DS1806 DIN input, which allows the controlling processor to read as well as write data or circularly clock
data through the daisy chain. The value of the feedback or isolation resistor should be in the range from 1
k
to 10 k.
To read data, the reading device configures itself as an input and monitors the state of the DIN line, which
is driven by COUT through the isolation resistor. When RST is driven high, bit 48 is present on the COUT
pin, which is fed back to the input DIN pin through the isolation resistor. When the CLK input transitions
low to high, bit 48 is loaded into the first position of the I/O shift register and bit 47 becomes present on
COUT and DIN of the next device. After 48 bits (or 48 times the number of the DS1806s in the daisy
chain), the data has shifted completely around and back to its original position. When RST transitions to
the low state to end data transfer, the value (the same as before the read occurred) is loaded in the shift
register.
ABSOLUTE AND RELATIVE LINEARITY
Absolute linearity is defined as the difference between the actual measured output voltage and the
expected output voltage. Absolute linearity is given in terms of a minimum increment or expected output
when the wiper is moved one position. The DS1806 is specified to have an absolute linearity of
±0.50
LSB.
Relative linearity is a measure of error between two adjacent wiper position points. The DS1806 is
specified to have a relative linearity of
±0.25 LSB.
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