Temperature-Controlled, NV, I2C, Logarithmic Resistor ___________________" />
參數(shù)資料
型號: DS1841N+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 5/17頁
文件大?。?/td> 0K
描述: IC RES LOG NV I2C 10-TDFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
接片: 128
電阻(歐姆): 22k
電路數(shù): 1
溫度系數(shù): 標(biāo)準(zhǔn)值 ±250 ppm/°C
存儲器類型: 非易失
接口: I²C,2 線串口
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 10-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 10-TDFN-EP(3x3)
包裝: 帶卷 (TR)
DS1841
Temperature-Controlled, NV, I2C,
Logarithmic Resistor
______________________________________________________________________________________
13
I2C Serial Interface Description
I2C Definitions
The following terminology is commonly used to describe
I2C data transfers. (See Figure 3 and I2C AC Electrical
Table for additional information.)
Master device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses and START and STOP conditions.
Slave devices: Slave devices send and receive data at
the master’s request.
Bus idle or not busy: Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic-high states.
START condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition.
STOP condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition.
Repeated START condition: The master can use a
repeated START condition at the end of one data trans-
fer to indicate that it will immediately initiate a new data
transfer following the current one. Repeated starts are
commonly used during read operations to identify a spe-
cific memory address to begin a data transfer. A repeat-
ed START condition is issued identically to a normal
START condition.
Bit write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements. Data is shifted into the
device during the rising edge of the SCL.
Bit read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time before the next rising edge of SCL during a
bit read. The device shifts out each bit of data on SDA
at the falling edge of the previous SCL pulse and the
data bit is valid at the rising edge of the current SCL
pulse. Remember that the master generates all SCL
clock pulses, including when it is reading bits from the
slave.
Acknowledge (ACK and NACK): An Acknowledge
(ACK) or Not Acknowledge (NACK) is always the 9th bit
transmitted during a byte transfer. The device receiving
data (the master during a read or the slave during a
write operation) performs an ACK by transmitting a 0
during the 9th bit. A device performs a NACK by trans-
mitting a 1 during the 9th bit. Timing for the ACK and
NACK is identical to all other bit writes. An ACK is the
acknowledgment that the device is properly receiving
data. A NACK is used to terminate a read sequence or
indicates that the device is not receiving data.
Byte write: A byte write consists of 8 bits of information
transferred from the master to the slave (most signifi-
cant bit first) plus a 1-bit acknowledgment from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgment is read using the bit read definition.
Registers 80h to C7h: Temperature Lookup Register (LUT)
FACTORY DEFAULT
00h
MEMORY TYPE
NV
80h
to
C7h
(See Table 3 for settings.)
Bit 7
Bit 0
These registers at location 80h to C7h are NV and serve to temperature compensate RW over the operating temperature
range of the DS1841.
The LUT entries are unsigned 8-bit values if the Adder Mode bit = 0. If the Adder Mode bit = 1, LUT entries are two’s
complement, signed 7-bit values.
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