Address Inputs, A0, A1, and A2, should be tied to either VCC or GND" />
參數(shù)資料
型號: DS1844E-100+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 2/14頁
文件大小: 0K
描述: IC POT DIG QUAD 100K 20-TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
接片: 64
電阻(歐姆): 100k
電路數(shù): 4
溫度系數(shù): 標(biāo)準(zhǔn)值 750 ppm/°C
存儲器類型: 易失
接口: 2 線串行(設(shè)備位址)或 5 線串行
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 帶卷 (TR)
DS1844
10 of 14
11.
Address Inputs, A0, A1, and A2, should be tied to either VCC or GND depending on the desired
address selections.
12.
Resistor inputs cannot go below GND by more than 0.5 volts or above VCC by more than 0.5
volts.
13.
-3dB cutoff frequency characteristics for the DS1844 depend on potentiometer total resistance:
DS1844-010; 1 MHz; DS1844-050; 200 kHz; DS1844-100; 100 kHz.
14.
See Figure 3, 5-wire timing diagram.
15.
For 5-wire control logic and VCC = 5V ±10%, maximum VIL = +0.8V. For VCC = 3.0V ±10%,VIL
= +0.6V.
16.
Absolute linearity is used to measure expected wiper voltage versus measured wiper voltage as
determined by wiper position. The DS1844 is specified to provide an absolute linearity of ± 0.5
LSB.
17.
Relative linearity is used to determine the change in wiper voltage between two adjacent wiper
positions. The DS1844 is specified to provide a relative linearity of ± 0.25 dB.
18.
When used as a rheostat or variable resistor the temperature coefficient applies: 650 ppm/°C.
When used as a voltage divider or potentiometer, the effective temperature coefficient approaches
30 ppm/°C.
19.
Maximum ICC active current is dependent on clock rates during serial port activity. Maximum
ICC active current is specified for 5 MHz clock rates, and worse case input logic levels.
20.
tSETUP is the minimum time required for the port select input, PS, to be stable before any activity
on SDA or SCL terminals.
21.
tSETUP is the minimum time required for the port select input, PS, and/or the R/ W input to be
stable before RST becomes active (or goes to a high state).
22.
See Figure 8, 5-wire timing diagram.
23.
Measured with load as shown in Figure 9.
24.
Valid for VCC = 5V only.
25.
Valid at 25
°C only.
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