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參數(shù)資料
| 型號： | DS1845E-010+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT/MEM DUAL NV 10K 14-TSSOP |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1,000 |
| 接片： | 100，256 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標準值 750 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
DS1845
12 of 14
AC ELECTRICAL CHARACTERISTICS
(-40°C to 85°C , Vcc=2.7V to 5.5V)
PARAMETER
SYMBOL CONDITION
MIN
TYP
MAX
UNITS NOTES
SCL clock frequency
fSCL
Fast Mode
Standard Mode
0
400
100
kHz
4
Bus free time between
STOP and START
condition
tBUF
Fast Mode
Standard Mode
1.3
4.7
ms
Hold time (repeated)
START condition
tHD:STA
Fast Mode
Standard Mode
0.6
4.0
ms
5
Low period of SCL clock
tLOW
Fast Mode
Standard Mode
1.3
4.7
ms
High period of SCL clock
tHIGH
Fast Mode
Standard Mode
0.6
4.0
ms
Data hold time
tHD:DAT
Fast Mode
Standard Mode
0
0.9
ms
6
Data set-up time
t
SU:DAT
Fast Mode
Standard Mode
100
250
ns
Start set-up time
tSU:STA
Fast Mode
Standard Mode
0.6
4.7
ms
Rise time of both SDA
and SCL signals
tR
Fast Mode
Standard Mode
20 +
0.1CB
300
1000
ns
7
Fall time of both SDA
and SCL signals
tF
Fast Mode
Standard Mode
20 +
0.1CB
300
ns
7
Set-up time for STOP
condition
tSU:STO
Fast Mode
Standard Mode
0.6
4.0
ms
Capacitive load for each
bus line
CB
400
pF
7
EEPROM write time
tW
5
ms
8
NOTES:
1. All voltages are referenced to ground.
2. ISTBY specified with VCC equal 3.0V and 5.0V and control port logic pins are driven to the appropriate
logic levels. Appropriate logic levels specify that logic inputs are within a 0.5V of ground or VCC for
the corresponding inactive state.
3. I/O pins of fast mode devices must not obstruct the SDA and SCL lines if VCC is switched off.
4. A fast mode device can be used in a standard mode system, but the requirement tSU:DAT > 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line tRMAX + tSU:DAT = 1000 + 250 = 1250 ns before the SCL line is released.
5. After this period, the first clock pulse is generated.
6. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the
SCL signal.
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| DS1845E-050/T&R | 制造商:Maxim Integrated Products 功能描述:DUAL NV POT & MEM TSSO T&R 10/50K - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC POT/MEM DUAL NV 50K 14-TSSOP |
| DS1845E-050/T&R | 功能描述:數(shù)字電位計 IC RoHS:否 制造商:Maxim Integrated 電阻:200 Ohms 溫度系數(shù):35 PPM / C 容差:25 % POT 數(shù)量:Dual 每 POT 分接頭:256 弧刷存儲器:Volatile 緩沖刷: 數(shù)字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作電源電壓:1.7 V to 5.5 V 電源電流:27 uA 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:TQFN-16 封裝:Reel |
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