參數(shù)資料
型號: DS1851E-010+
廠商: Maxim Integrated Products
文件頁數(shù): 9/18頁
文件大小: 0K
描述: IC DAC DUAL NV TEMP CNTRL 8TSSOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 96
位數(shù): 8
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
工作溫度: -40°C ~ 95°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 8-TSSOP
包裝: 管件
輸出數(shù)目和類型: 2 電壓,單極
采樣率(每秒): *
DS1851
17 of 18
NOTES:
1. All voltages are referenced to ground.
2. A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
> 250ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line tRMAX + t
SU:DAT
= 1000 + 250 = 1250ns before the SCL line is released.
3. After this period, the first clock pulse is generated.
4. The maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the
SCL signal.
5. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the
VI
H MIN
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
6. C
B
- total capacitance of one bus line in pF, timing referenced to (0.9)(V
CC
) and (0.1)(V
CC
).
7. EEPROM-write begins after a STOP condition occurs.
8. Measured with SDA = SCL = Vrc = VCC, and Vrg = GND. The outputs OutV and OutG are left open.
9. Valid at 25°C only.
10. With Vrc = VCC -1.25 and Vrg = 1.25 + GND.
11. 0.8% is equivalent to 2 LSB.
PACKAGE INFORMATION
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a
different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
8 TSSOP
H8+1
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