參數(shù)資料
型號(hào): DS1852B-000+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 2/26頁
文件大?。?/td> 0K
描述: IC MONITOR TXRX OPTICAL 25-BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 收發(fā)器
電源電壓: 2.7 V ~ 5.5 V
安裝類型: 表面貼裝
封裝/外殼: 25-TFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 25-BGA(5x5)
包裝: 帶卷 (TR)
DS1852
10 of 26
Once the device address is clocked in and acknowledged by the DS1852 with the R/W bit set to high,
the current address data word is clocked out. The master does not respond with a zero, but does generate
a stop condition afterwards.
RANDOM READ
A random read requires a dummy byte write sequence to load in the data word address. Once the device
and data address bytes are clocked in by the master, and acknowledged by the DS1852, the master must
generate another start condition. The master now initiates a current address read by sending the device
address with the R/W bit set high. The DS1852 will acknowledge the device address and serially clocks
out the data byte.
SEQUENTIAL ADDRESS READ
Sequential reads are initiated by either a current address read or a random address read. After the master
receives the first data byte, the master responds with an acknowledge. As long as the DS1852 receives
this acknowledge after a byte is read, the master may clock out additional data words from the DS1852.
After reaching address FFh, it resets to address 00h.
The sequential read operation is terminated when the master initiates a stop condition. The master does
not respond with a zero.
For a more detailed description of 2-wire theory of operation, see 2-WIRE SERIAL PORT OPERATION.
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