參數(shù)資料
型號: DS1856E-030+
廠商: Maxim Integrated Products
文件頁數(shù): 26/31頁
文件大?。?/td> 0K
描述: IC RES TEMP-CNTRL 30/10K 16TSSOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 96
接片: 256
電阻(歐姆): 10k,30k
電路數(shù): 2
溫度系數(shù): 標準值 50 ppm/°C
存儲器類型: 非易失
接口: 2 線串口
電源電壓: 2.85 V ~ 5.5 V
工作溫度: -40°C ~ 95°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
4
Maxim Integrated
DS1856
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Fast mode
0
400
SCL Clock Frequency (Note 9)
fSCL
Standard mode
0
100
kHz
Fast mode
1.3
Bus Free Time Between STOP and
START Condition (Note 9)
tBUF
Standard mode
4.7
s
Fast mode
0.6
Hold Time (Repeated)
START Condition (Notes 9, 10)
tHD:STA
Standard mode
4.0
s
Fast mode
1.3
LOW Period of SCL Clock (Note 9)
tLOW
Standard mode
4.7
s
Fast mode
0.6
HIGH Period of SCL Clock (Note 9)
tHIGH
Standard mode
4.0
s
Fast mode
0
0.9
Data Hold Time (Notes 9, 11, 12)
tHD:DAT
Standard mode
0
s
Fast mode
100
Data Setup Time (Note 9)
tSU:DAT
Standard mode
250
ns
Fast mode
0.6
START Setup Time (Note 9)
tSU:STA
Standard mode
4.7
s
Fast mode
20 + 0.1CB
300
Rise Time of Both SDA and SCL
Signals (Note 13)
tR
Standard mode
20 + 0.1CB
1000
ns
Fast mode
20 + 0.1CB
300
Fall Time of Both SDA and SCL
Signals (Note 13)
tF
Standard mode
20 + 0.1CB
300
ns
Fast mode
0.6
Setup Time for STOP Condition
tSU:STO
Standard mode
4.0
s
Capacitive Load for Each Bus Line
CB
(Note 13)
400
pF
EEPROM Write Time
tW
10
20
ms
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.85V to 5.5V, TA = -40°C to +95°C, unless otherwise noted. See Figure 6.)
Note 1:
All voltages are referenced to ground.
Note 2:
I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if VCC is switched off.
Note 3:
SDA and SCL are connected to VCC and all other input signals are connected to well-defined logic levels.
Note 4:
Full scale is user programmable. The maximum voltage that the MON inputs read is approximately full scale, even if the volt-
age on the inputs is greater than full scale.
Note 5:
This voltage defines the maximum range of the analog-to-digital converter voltage, not the maximum VCC voltage.
Note 6:
Absolute linearity is the difference of measured value from expected value at DAC position. The expected value is a
straight line from measured minimum position to measured maximum position.
Note 7:
Relative linearity is the deviation of an LSB DAC setting change vs. the expected LSB change. The expected LSB change
is the slope of the straight line from measured minimum position to measured maximum position.
Note 8:
See the
Typical Operating Characteristics.
Note 9:
A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met. This
is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000ns + 250ns = 1250ns
before the SCL line is released.
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