參數(shù)資料
型號: DS1857E-050+
廠商: Maxim Integrated Products
文件頁數(shù): 4/22頁
文件大小: 0K
描述: IC RES TEMP 50/50K 2MON 16-TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 96
接片: 256
電阻(歐姆): 50k
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 50 ppm/°C
存儲器類型: 非易失
接口: I²C(設(shè)備位址)
電源電壓: 3 V ~ 5.5 V
工作溫度: -40°C ~ 95°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
DS1857
Register Map
A description of the registers is below. The registers
are read only (R) or read/write (R/W). The R/W registers
are writable only if write protect has not been asserted
(see the Memory Description section).
Dual Temperature-Controlled Resistors with
External Temperature Input and Monitors
12
____________________________________________________________________
MEMORY LOCATION
(hex)
EEPROM/SRAM
R/W
DEFAULT SETTING
(hex)
NAME OF LOCATION
FUNCTION
00 to 7F
EEPROM
R/W
00
Standards Data
Auxiliary Device
MEMORY
LOCATION
(hex)
EEPROM/
SRAM
R/W
DEFAULT
SETTING
(hex)
NAME OF LOCATION
FUNCTION
00 to 01
EEPROM
R/W
00
TMPlimhi (MSB to LSB)
Contains upper limit settings for temperature.
If the limit is violated, a flag in Main Device
byte 70h is set.
02 to 03
EEPROM
R/W
00
TMPlimlo (MSB to LSB)
Contains lower limit settings for temperature. If
the limit is violated, a flag in Main Device byte
70h is set.
04 to 07
EEPROM
R
00
Reserved
08 to 09
EEPROM
R/W
00
VCClimhi (MSB to LSB)
Contains upper limit settings for VCC. If the
limit is violated, a flag in Main Device byte 70h
is set.
0A to 0B
EEPROM
R/W
00
VCClimlo (MSB to LSB)
Contains lower limit settings for VCC. If the
limit is violated, a flag in Main Device byte 70h
is set.
0C to 0F
EEPROM
00
Reserved
10 to 11
EEPROM
R/W
00
MON1limhi (MSB to LSB)
Contains upper limit settings for MON1. If the
limit is violated, a flag in Main Device byte 70h
is set.
12 to 13
EEPROM
R/W
00
MON1limlo (MSB to LSB)
Contains lower limit settings for MON1. If the
limit is violated, a flag in Main Device byte 70h
is set.
14 to 17
EEPROM
00
Reserved
18 to 19
EEPROM
R/W
00
MON2limhi (MSB to LSB)
Contains upper limit settings for MON2. If the
limit is violated, a flag in Main Device byte 70h
is set.
1A to 1B
EEPROM
R/W
00
MON2limlo (MSB to LSB)
Contains lower limit settings for MON2. If the
limit is violated, a flag in Main Device byte 70h
is set.
Main Device
Note: SRAM defaults are power-on defaults. EEPROM defaults are factory defaults.
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