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參數(shù)資料
| 型號： | DS1868N-050 |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | Digital Potentiometer |
| 中文描述： | 數(shù)字電位器 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 300K |
| 代理商： | DS1868N-050 |
DS1867
5 of 14
102199
I/O SHIFT REGISTER
Figure 3
17-BIT I/O SHIFT REGISTER
Transmission of data always begins with the stack select bit followed by the potentiometer-1 wiper
position value and lastly the potentiometer-0 wiper position value (see Figure 2(a)).
When wiper position data is to be written to the DS1867, 17-bits (or some integer multiple) of data should
always be transmitted. Transactions which do not send a complete 17-bits (or multiple) will leave the
register incomplete and possibly an error in desired wiper position. After a communication transaction
has been completed the
RST
signal input should be taken to a low state to prevent any inadvertent
changes to the device shift register. Once
RST
has reached a low state, the contents of the I/O shift
register are loaded into the respective multiplexers for setting wiper position. A new wiper position will
only engage pending a
RST
transition to the low state. The wiper position for the high-end terminals H0
and H1 will have data values FF (hex), while the low-end terminals will have data values 00 (hex).
STACKED CONFIGURATION
The potentiometers of the DS1867 can be connected in series as shown in Figure 4. This is referred to as
the stacked configuration and allows the user to double the total end-to-end resistance of the part. The
resolution of the combined potentiometers will remain the same as a single potentiometer but with a total
of 512 wiper positions available. Device resolution is defined as R
TOT
/256 (per potentiometer); where
R
TOT
is equal to the device resistance value. The wiper output for the combined stacked potentiometer will
be taken at the S
out
pin, which is the multiplexed output of the wiper of potentiometer-0 (W0) or
potentiometer-1 (W1). The potentiometer wiper selected at the S
out
output is governed by the setting of
the stack select bit (bit-0) of the 17-bit I/O shift register. If the stack select bit has value 0, the multiplexed
output, S
out
, will be that of the potentiometer-0 wiper. If the stack select bit has value 1, the multiplexed
output, S
out
, will be that of the potentiometer-1 wiper.
STACKED CONFIGURATION
Figure 4
CASCADE OPERATION
A feature of the DS1867 is the ability to control multiple devices from a single processor. Multiple
DS1867s can be linked or daisy-chained as shown in Figure 5. As a data bit is entered into the I/O shift
register of the DS1867 it will appear at the C
out
output after a maximum delay of 70 nanoseconds.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1868N-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Potentiometer |
| DS1868S-010 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Potentiometer |
| DS1868S-010+T&R | 制造商:Maxim Integrated Products 功能描述:- Tape and Reel |
| DS1868S-050 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Potentiometer |
| DS1868S-050/T&R | 制造商:Maxim Integrated Products 功能描述:DUAL DIG. POT 16P SOIC 50K T&R - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC DGTL POT 50K 2CH 16SOIC |
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