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參數(shù)資料
| 型號： | DS1882Z-050+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DIGIT DL LOG 50K 16SOIC |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 接片： | 64 |
| 電阻（歐姆）： | 45k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標準值 750 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設備位址） |
| 電源電壓： | 4.5 V ~ 7 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
DS1882
Dual Log Audio Digital Potentiometer
12
____________________________________________________________________
Writing Command Byte Values
An example of writing to the DS1882 is shown in Figure 2.
The DS1882 has one write command that is used to
change the Potentiometer Wiper Setting Registers and
the Configuration Register. All write operations begin with
a START from the master, followed by a slave address
byte. The R/W bit should be written to 0, which initiates
a write command. Once the slave address byte has
been issued and the master receives the acknowledge
from the DS1882, potentiometer wiper data is transmit-
ted to the DS1882 by the master device.
If the potentiometer has been configured to be written
in nonvolatile memory (see the Configuration Register
section), then the acknowledge needs to be followed
with a STOP command. This command is required from
the master at the end of data transmission to initiate the
EEPROM write. The STOP command is also accepted if
the user has configured the pot values to be written in
volatile memory, but no EEPROM is written to.
I2C Serial Interface Description
I2C interface supports a bidirectional data transmission
protocol with device addressing. A device that sends
data on the bus is defined as a transmitter, and a
device receiving data as a receiver. The device that
controls the message is called a master. The devices
that are controlled by the master are slaves. The bus
must be controlled by a master device that generates
the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions. The
DS1882 operates as a slave on the I2C bus. Connections
to the bus are made by the open-drain I/O lines, SDA
and SCL. The following I/O terminals control the I2C
serial port: CE, SDA, SCL, A0, A1, and A2. A data
transfer protocol and a timing diagram are provided in
Figures 3 and 4. The following terminology is commonly
used to describe I2C data transfers.
I2C Definitions
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, START and STOP conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic-high states. When the bus is idle it often initi-
ates a low-power mode for slave devices.
START Condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition. See the timing dia-
gram for applicable timing.
STOP Condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition. See the timing dia-
gram for applicable timing.
Repeated START Condition: The master can use a
repeated START condition at the end of one data trans-
fer to indicate that it will immediately initiate a new data
transfer following the current one. Repeated STARTs
are commonly used during read operations to identify a
specific memory address to begin a data transfer. A
repeated START condition is issued identically to a nor-
mal START condition. See the timing diagram for
applicable timing.
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold-time requirements (see Figure 4). Data is
shifted into the device during the rising edge of the SCL.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
WRITE PROTOCOL
0
MSB
LSB
POT-0
1
0
MSB
LSB
POT-1
A
0
A
1
A
2
0
101
0
MSB
LSB
R/W = 0
DATA BYTES CAN BE WRITTEN IN ANY ORDER.
COMMAND
BYTE
COMMAND
BYTE
COMMAND
BYTE
SLAVE ADDRESS
BYTE
MSB
LSB
CONFIG
REG
10
ST
AR
T
ACK
STOP
Figure 2. Write Protocol
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