DS1963S
30 of 37
correct ROM and memory function command. In a mixed population network, the reset low time t
RSTL
needs to be long enough for the slowest 1-Wire slave device to recognize it as a reset pulse. This duration
is 480μs at standard speed and 48μs at Overdrive speed. If the bus master uses slew-rate control on the
falling edge, it must pull down the line for t
RSTL
+ t
F
to compensate for the edge. A t
RSTL
duration of
480μs or longer will exit the Overdrive Mode returning the device to standard speed. If the DS1963S is in
Overdrive Mode and t
RSTL
is no longer than 80μs, the device will remain in Overdrive Mode.
After the bus master has released the line it goes into receive mode (RX). Now, the 1-Wire bus is pulled
to V
PUP
via the pullup resistor or, in case of a DS2480B driver, by active circuitry. When the threshold
V
TH
is crossed, the DS1963S waits for t
PDH
and then transmits a Presence Pulse by pulling the line low for
t
PDL
. To detect a presence pulse, the master must test the logical state of the 1-Wire line at t
MSP
.
The t
RSTH
window must be at least the sum of t
PDHMAX
, t
PDLMAX
, and t
RECMIN
. Immediately after t
RSTH
is
expired, the DS1963S is ready for data communication. In a mixed population network, t
RSTH
should be
extended to minimum 480μs at standard speed and 48μs at Overdrive speed to accommodate other 1-
Wire devices.
INITIALIZATION PROCEDURE (RESET AND PRESENCE PULSES)
Figure 11
RESISTOR
MASTER
DS1963S
t
RSTL
t
PDL
t
RSTH
t
PDH
MASTER TX RESET PULSE
MASTER RX PRESENCE PULSE
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
t
F
t
REC
t
MSP
Read/Write Time Slots
Data communication with the DS1963S takes place in time slots that carry a single bit each. Write time
slots transport data from bus master to slave. Read time-slots transfer data from slave to master. The
definitions of the write and read time slots are illustrated in Figure 12.
All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line
falls below the threshold V
TL
, the DS1963S starts its internal timing generator that determines when the
data line will be sampled during a write time slot and how long data will be valid during a read time slot.
Master to Slave
For a
write-one
time slot, the voltage on the data line must have crossed the V
THMAX
threshold after the
write-one low time t
W1LMAX
is expired. For a
write-zero
time slot, the voltage on the data line must stay
below the V
THMIN
threshold until the write-zero low time t
W0LMIN
is expired. For most reliable
communication the voltage on the data line should not exceed V
ILMAX
during the entire t
W0L
window.
After the V
THMAX
threshold has been crossed, the DS1963S needs a recovery time t
REC
before it is ready
for the next time slot.