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參數(shù)資料
| 型號： | DS21348G+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/76頁 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/E1/J1 3.3V 49-BGA |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 416 |
| 類型： | 線路接口裝置（LIU） |
| 驅動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | T1/E1/J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 49-LFBGA，CSPBGA |
| 供應商設備封裝： | 49-CSBGA（7x7） |
| 包裝： | 托盤 |
| 產品目錄頁面： | 1429 (CN2011-ZH PDF) |
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DS21348/DS21Q348
14 of 76
2.1 Pin Descriptions
Table 2-5. Pin Descriptions in Parallel Port Mode (Sorted by Pin Name,
DS21348T Pin Numbering)
NAME
PIN
I/O
FUNCTION
A0 to A4
11 to 7
I
Address Bus. In nonmultiplexed bus operation (BIS1 = 0, BIS0 =
1), serves as the address bus. In multiplexed bus operation (BIS1 =
0, BIS0 = 0), these pins are not used and should be tied low.
ALE (AS)
4
I
Address Latch Enable (Address Strobe). When using the parallel
port (BIS1 = 0) in multiplexed bus mode (BIS0 = 0), serves to
demultiplex the bus on a positive-going edge. In nonmultiplexed bus
mode (BIS0 = 1), should be tied low.
BIS0/BIS1
32/33
I
Bus Interface Select Bits 0 and 1. Used to select bus interface
option. See Table 2-1 for details.
BPCLK
31
O
Backplane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz clock output that is referenced to RCLK selectable via
CCR5.7 and CCR5.6. In hardware mode, defaults to 16.384MHz
output.
CS
1
I
Chip Select, Active Low. This active-low signal must be low to
read or write to the device.
D0/AD0 to
D7/AD7
19 to 12
I/O
Data Bus/Address/Data Bus. In nonmultiplexed bus operation
(BIS1 = 0, BIS0 = 1), serves as the data bus. In multiplexed bus
operation (BIS1 = 0, BIS0 = 0), serves as an 8-bit multiplexed
address/data bus.
HRST
29
I
Hardware Reset, Active Low. Bringing
HRST low resets the
DS21348, setting all control bits to their default state of all zeros.
INT
23
O
Interrupt, Active Low. Flags host controller during conditions and
change of conditions defined in the Status Register. Active low,
open drain output.
MCLK
30
I
Master Clock. A 2.048MHz (±50ppm) clock source with TTL
levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz
clock source is optional.
N/A
—
I
Not Assigned. Should be tied low.
PBEO
24
O
PRBS Bit Error Output. The receiver will constantly search for a
215-1 or a 220-1 PRBS depending on the ETS bit setting (CCR1.7).
Remains high if out of synchronization with the PRBS pattern. Goes
low when synchronized to the PRBS pattern. Any errors in the
received pattern after synchronization will cause a positive going
pulse (with same period as E1 or T1 clock) synchronous with
RCLK. PRBS bit errors can also be reported to the ECR1 and ECR2
registers by setting CCR6.2 to a logic 1.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS21348G+ | 功能描述:網(wǎng)絡控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21348G+W | 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21348GB | 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21348GN | 功能描述:網(wǎng)絡控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21348GN+ | 功能描述:網(wǎng)絡控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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