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參數(shù)資料
| 型號(hào)： | DS21348G |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 41/76頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1/J1 3.3V 49-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 416 |
| 類(lèi)型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | T1/E1/J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 49-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 49-CSBGA（7x7） |
| 包裝： | 托盤(pán) |
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DS21348/DS21Q348
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6.2 Loopbacks
6.2.1 Remote Loopback (RLB)
When RLB (CCR6.6) is enabled, the DS21348 is placed into remote loopback. In this loopback, data
from the clock/data recovery state machine will be looped back to the transmit path passing through the
jitter attenuator if it is enabled. The data at the RPOS and RNEG pins will be valid while data presented
at TPOS and TNEG will be ignored. See Figure 1-1 for details.
If the Automatic Remote Loop Back Enable (CCR6.5) is set to a one, the DS21348 will automatically go
into remote loop back when it detects the loop-up code programmed in the Receive Up Code Definition
Registers (RUPCD1 and RUPCD2) for a minimum of 5 seconds. When the DS21348 detects the loop
down code programmed in the Receive Loop-Down Code Definition registers (RDNCD1 and RDNCD2)
for a minimum of 5 seconds, the DS21348 will come out of remote loop back. The ARLB can also be
disabled by setting ARLBE to a zero.
6.2.2 Local Loopback (LLB)
When LLB (CCR6.7) is set to a one, the DS21348 is placed into Local Loopback. In this loopback, data
on the transmit-side will continue to be transmitted as normal. TCLK and TPOS/TNEG will pass through
the jitter attenuator (if enabled) and be output at RCLK and RPOS/RNEG. Incoming data from the line at
RTIP and RRING will be ignored. If Transmit Unframed All Ones (CCR3.7) is set to a one while in LLB,
TTIP and TRING will transmit all ones while TCLK and TPOS/TNEG will be looped back to RCLK and
RPOS/RNEG. See Figure 1-1 for more details.
6.2.3 Analog Loopback (ALB)
Setting ALB (CCR6.4) to a one puts the DS21348 in Analog Loopback. Signals at TTIP and TRING will
be internally connected to RTIP and RRING. The incoming signals at RTIP and RRING will be ignored.
The signals at TTIP and TRING will be transmitted as normal. See Figure 1-1 for more details.
6.2.4 Dual Loopback (DLB)
Setting both CCR6.7 and CCR6.6 to a one, LLB and RLB respectively, puts the DS21348 into Dual
Loopback operation. The TCLK and TPOS/TNEG signals will be looped back through the jitter
attenuator (if enabled) and output at RCLK and RPOS/RNEG. Clock and data recovered from RTIP and
RRING will be looped back to the transmit-side and output at TTIP and TRING. This mode of operation
is not available when implementing hardware operation. See Figure 1-1 for more details.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21348G+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21348G+W | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21348GB | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21348GN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21348GN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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