參數(shù)資料
型號: DS21372T
廠商: Maxim Integrated Products
文件頁數(shù): 20/22頁
文件大?。?/td> 0K
描述: IC TESTER BIT ERROR 3.3V 32-TQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
產(chǎn)品變化通告: Product Discontinuation 20/Feb/2012
標準包裝: 250
功能: 位誤碼率測試器(BERT)
接口: T1
電路數(shù): 1
電源電壓: 3 V ~ 3.6 V
電流 - 電源: 10mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 32-TQFP
供應商設備封裝: 32-TQFP(7x7)
包裝: 托盤
包括: 錯誤計數(shù)器,樣式發(fā)生器和檢測器
DS21372
7 of 22
PLR: PATTERN LENGTH REGISTER (ADDRESS=04 HEX)
(MSB)
(LSB)
-
LB4
LB3
LB2
LB1
LB0
SYMBOL
POSITION
NAME AND DESCRIPTION
-
PLR1.7
Not Assigned. Should be set to 0 when written to.
-
PLR1.6
Not Assigned. Should be set to 0 when written to.
-
PLR1.5
Not Assigned. Should be set to 0 when written to.
LB4
PLR1.4
Length Bit 4.
LB3
PLR1.3
Length Bit 3.
LB2
PLR1.2
Length Bit 2.
LB1
PLR1.1
Length Bit 1.
LB0
PLR1.0
Length Bit 0.
5. POLYNOMIAL TAP REGISTER
Polynomial Tap Bits PT4 - PT0 determine the feedback position of Tap B connected to the XOR input of
the pattern generator. Feedback Tap B provides one of two feedback paths within the pattern generator.
Please refer to Figure 2 for a block diagram of the pattern generator and to Tables 4 and 5 for register
programming examples.
PTR: POLYNOMIAL TAP REGISTER (ADDRESS=05 HEX)
(MSB)
(LSB)
-
PT4
PT3
PT2
PT1
PT0
SYMBOL
POSITION
NAME AND DESCRIPTION
-PTR.7
Not Assigned. Should be set to 0 when written to.
-PTR.6
Not Assigned. Should be set to 0 when written to.
-PTR.5
Not Assigned. Should be set to 0 when written to.
PT4
PTR.4
Polynomial Tap Bit 4.
PT3
PTR.3
Polynomial Tap Bit 3.
PT2
PTR.2
Polynomial Tap Bit 2.
PT1
PTR.1
Polynomial Tap Bit 1.
PT0
PTR.0
Polynomial Tap Bit 0.
6. PATTERN CONTROL REGISTER
The Pattern Control Register (PCR) is used to configure the operating parameters of the DS21372 and to
control the patterns being generated and received. Also the PCR is used to control the pattern
synchronizer and the error and bit counters.
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