參數(shù)資料
型號(hào): DS2141A
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 17/39頁(yè)
文件大?。?/td> 0K
描述: IC CONTROLLER T1 5V 40-DIP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 10
控制器類型: T1 控制器
接口: 并行/串行
電源電壓: 4.5 V ~ 5.5 V
電流 - 電源: 10mA
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 40-DIP(0.600",15.24mm)
供應(yīng)商設(shè)備封裝: 40-PDIP
包裝: 管件
DS2141A
24 of 39
TTR1/TTR2/TTR3: TRANSMIT TRANSPARENCY REGISTERS (39h to 3Bh)
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TTR1 (39)
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TTR2 (3A)
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TTR3 (3B)
SYMBOL
POSITION
NAME AND DESCRIPTION
CH24
CH1
TTR3.7
TTR1.0
Transmit Transparency Registers.
0=this DS0 channel is not transparent.
1=this DS0 channel is transparent.
Each of the bit positions in the Transmit Transparency Registers (TTR1/TTR2/TTR3) represents a DS0
channel in the outgoing frame. When these bits are set to a 1, the corresponding channel is transparent (or
clear). If a DS0 is programmed to be clear, no robbed bit signaling will be inserted nor will the channel
have bit 7 stuffing performed. However, in the D4 framing mode, bit 2 will be overwritten by a 0 when a
Yellow Alarm is transmitted.
TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS (3Ch to 3Eh)
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TIR1 (3C)
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TIR2 (3D)
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TIR3 (3E)
SYMBOL
POSITION
NAME AND DESCRIPTION
CH24
TTR3.7
Transmit Idle Registers.
0=do not insert the Idle Code into this DS0 channel.
CH1
TTR1.0
1=insert the Idle Code into this channel.
TIDR: TRANSMIT IDLE DEFINITION REGISTER (3Fh)
(MSB)
(LSB)
TIDR7
TIDR6
TIDR5
TIDR4
TIDR3
TIDR2
TIDR1
TIDR0
SYMBOL
POSITION
NAME AND DESCRIPTION
TIDR7
TIDR.7
MSB of the Idle Code.
TIDR0
TIDR.0
LSB of the Idle Code.
Each of the bit positions in the Transmit Idle Registers (TIR1/TIR2/TIR3) represents a DS0 channel in
the outgoing frame. When these bits are set to a 1, the corresponding channel will transmit the Idle Code
contained in the Transmit Idle Definition Register (TIDR). Robbed bit signaling and bit 7 stuffing will
occur over the programmed Idle Code unless the DS0 channel is made transparent by the Transmit
Transparency Registers.
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