參數(shù)資料
型號(hào)： DS2143Q/T&R
廠(chǎng)商： Maxim Integrated Products
文件頁(yè)數(shù)： 34/44頁(yè)
文件大?。?/td> 0K
描述： IC CONTROLLER E1 5V LP 44-PLCC
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 500
控制器類(lèi)型： E1 控制器
接口： 并行/串行
電源電壓： 4.5 V ~ 5.5 V
電流 - 電源： 10mA
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線(xiàn)）
供應(yīng)商設(shè)備封裝： 44-PLCC（16.59x16.59）
包裝： 帶卷 (TR)
DS2143/DS2143Q
4 of 44
PIN DESCRIPTION Table 1
PIN
SYMBOL
TYPE
DESCRIPTION
1TCLK
I
Transmit Clock. 2.048 MHz primary clock. A clock must be
applied at the TCLK pin for the parallel port to operate properly.
2TSER
I
Transmit Serial Data. Transmit NRZ serial data, sampled on the
falling edge of TCLK.
3TCHCLK
O
Transmit Channel Clock. 256 kHz clock which pulses high during
the LSB of each channel. Useful for parallel-to-serial conversion of
channel data. See Section 13 for timing details.
4
5
TPOS
TNEG
O
Transmit Bipolar Data. Updated on rising edge of TCLK. For
optical links, can be programmed to output NRZ data.
6-13
AD0-AD7
I/O
Address/Data Bus. An 8-bit multiplexed address/data bus.
14
BTS
I
Bus Type Select. Strap high to select Motorola bus timing; strap
low to select Intel bus timing. This pin controls the function of
RD
(DS), ALE(AS), and WR (R/ W ) pins. If BTS=1, then these pins
assume the function listed in parentheses ().
15
RD
(DS)
I
Read Input (Data Strobe).
16
CS
I
Chip Select. Must be low to read or write the port.
17
ALE(AS)
I
Address Latch Enable (Address Strobe). A positive-going edge
serves to demultiplex the bus.
18
WR
(R/ W )
I
Write Input (Read/Write).
19
RLINK
O
Receive Link Data. Outputs Sa bits. See Section 13 for timing
details.
20
VSS
-
Signal Ground. 0.0 volts.
21
RLCLK
O
Receive Link Clock. 4 kHz to 20 kHz demand clock for the
RLINK output. Controlled by RCR2. See Section 13 for timing
details.
22
RCLK
I
Receive Clock. 2.048 MHz primary clock. A clock must be applied
at the RCLK pin for the parallel port to operate properly.
23
RCHCLK
O
Receive Channel Clock. 256 kHz clock which pulses high during
the LSB of each channel. Useful for serial to parallel conversion of
channel data. See Section 13 for timing details.
24
RSER
O
Receive Serial Data. Received NRZ serial data, updated on rising
edges of RCLK.
25
RSYNC
I/O
Receive Sync. An extracted pulse, one RCLK wide, is output at this
pin which identifies either frame (RCR1.6=0) or multiframe
boundaries (RCR1.6=1). If the elastic store is enabled via the
RCR2.1, then this pin can be enabled to be an input via RCR1.5 at
which a frame boundary pulse is applied. See Section 13 for timing
details.
26
27
RPOS
RNEG
I
Receive Bipolar Data Inputs. Sampled on falling edge of RCLK.
Tie together to receive NRZ data and disable BPV monitoring
circuitry.
28
SYSCLK
I
System Clock. 1.544 MHz or 2.048 MHz clock. Only used when
the elastic store function is enabled via the RCR2.1. Should be tied
low in applications that do not use the elastic store.
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