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參數(shù)資料
| 型號： | DS21448GN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 41/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU QUAD E1/T1 144-BGA |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 90 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 4/4 |
| 規(guī)程： | T1/E1/J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-BGA |
| 供應(yīng)商設(shè)備封裝： | 144-TEPBGA（17x17） |
| 包裝： | 管件 |
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DS21448 3.3V T1/E1/J1 Quad Line Interface
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EXTEST. This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the
instruction register, the following actions occur. Once enabled through the update-IR state, the parallel outputs of
all digital output pins are driven. The boundary scan register is connected between JTDI and JTDO. The capture-
DR samples all digital inputs into the boundary scan register.
CLAMP. All digital outputs of the device are output data from the boundary scan parallel output while connecting
the bypass register between JTDI and JTDO. The outputs do not change during the CLAMP instruction.
HIGHZ. All digital outputs of the device are placed in a high-impedance state. The BYPASS register is connected
between JTDI and JTDO.
IDCODE. When the IDCODE instruction is latched into the parallel instruction register, the identification test
register is selected. The device identification code is loaded into the identification register on the rising edge of
JTCLK following entry into the capture-DR state. Shift-DR can be used to shift the identification code out serially
through JTDO. During test-logic-reset, the identification code is forced into the instruction register’s parallel output.
The ID code always has a 1 in the LSB position. The next 11 bits identify the manufacturer’s JEDEC number and
number of continuation bytes followed by 16 bits for the device and 4 bits for the version Table 8-B. Table 8-C lists
the device ID code for the SCT devices.
Table 8-B. ID Code Structure
MSB
LSB
Version
(Contact Factory)
Device ID
JEDEC
1
4 bits
16 bits
00010100001
1
Table 8-C. Device ID Codes
DEVICE
16-BIT ID
DS21448
0018
8.3 Test Registers
IEEE 1149.1 requires a minimum of two test registers—the bypass register and the boundary scan register. An
optional test register, the identification register, has been included with the DS21448 design. It is used with the
IDCODE instruction and the test-logic-reset state of the TAP controller.
Bypass Register
The bypass register is a single 1-bit shift register used with the BYPASS, CLAMP, and HIGHZ instructions that
provides a short path between JTDI and JTDO.
Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is
selected during the IDCODE instruction and when the TAP controller is in the test-logic-reset state. See Table 8-B
and Table 8-C for more information about bit usage.
Boundary Scan Register
The boundary scan register contains a shift register path and a latched parallel output for all control cells and digital
I/O cells, and is n bits in length. See Table 8-D for all cell bit locations and definitions.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21448GN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21448L | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21448L+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21448L+W | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21448LDK | 功能描述:KIT DESIGN LIU DS21448L T1/J1/E1 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標準包裝:1 系列:- 傳感器類型:CMOS 成像，彩色（RGB） 傳感范圍:WVGA 接口:I²C 靈敏度:60 fps 電源電壓:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相關(guān)產(chǎn)品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
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