- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16261 > DS2148DK (Maxim Integrated Products)KIT DESIGN LIU DS2148 3/5V T1/E1 PDF資料下載
參數(shù)資料
| 型號： | DS2148DK |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 41/73頁 |
| 文件大小： | 0K |
| 描述： | KIT DESIGN LIU DS2148 3/5V T1/E1 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 電信，線路接口單元（LIU） |
| 已用 IC / 零件： | DS2148 |
| 已供物品： | 板 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁當(dāng)前第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁
DS2148/DS21Q48
46 of 73
7 ANALOG INTERFACE
7.1 Receiver
The DS2148 contains a digital clock recovery system. The DS2148 couples to the receive E1 or T1
twisted pair (or coaxial cable in 75 E1 applications) via a 1:1 transformer. See Table 7-3 or transformer
termination requirements. The DS2148 has the option of using internal termination resistors.
The DS2148 is designed to be fully software-selectable for E1 and T1 without the need to change any
external resistors for the receive-side. The receive-side will allow the user to configure the DS2148 for
75, 100, or 120 receive termination by setting the RT1 (CCR5.1) and RT0 (CCR5.0) bits. When
using the internal termination feature, the Rr resistors should be 60 each (Figure 7-1). If external
termination is required, RT1 and RT0 should be set to 0 and both Rr resistors in Figure 7-1 will need to
be 37.5, 50, or 60 each depending on the line impedance.
The resultant E1 or T1 clock derived from the 2.048/1.544 PLL (JACLK in Figure 1-1) is internally
multiplied by 16 via another internal PLL and fed to the clock recovery system. The clock recovery
system uses the clock from the PLL circuit to form a 16 times oversampler, which is used to recover the
clock and data. This oversampling technique offers outstanding performance to meet jitter tolerance
specifications shown in Figure 7-6.
Normally, the clock that is output at the RCLK pin is the recovered clock from the E1 AMI/HDB3 or T1
AMI/B8ZS waveform presented at the RTIP and RRING inputs. When no signal is present at RTIP and
RRING, a Receive Carrier Loss (RCL) condition will occur and the RCLK will be derived from the
JACLK source (Figure 1-1). If the jitter attenuator is placed in the receive path (as is the case in most
applications), the jitter attenuator restores the RCLK to an approximate 50% duty cycle. If the jitter
attenuator is either placed in the transmit path or is disabled, the RCLK output can exhibit slightly shorter
high cycles of the clock. This is due to the highly oversampled digital clock recovery circuitry. See the
Receive AC Timing Characteristics in Section 10 for more details.
The receive-side circuitry also contains a clock synthesizer, which outputs a user configurable clock (up
to 16.384MHz) synthesized to RCLK at BPCLK (pin 31). See Table 4-3 for details on output clock
frequencies at BPCLK. In hardware mode, BPCLK defaults to a 16.384MHz output.
The DS2148 has a bypass mode for the receive side clock and data. This allows the BPCLK to be derived
from RCLK after the jitter attenuator while the clock and data presented at RCLK, RPOS, and RNEG go
unaltered. This is intended for applications where the receive side jitter attenuation will be done after the
LIU. Setting RJAB (CCR6.3) to a logic 1 will enable the bypass. Be sure that the jitter attenuator is in the
receive path (CCR4.3 = 0). See Figure 1-1 for details.
The DS2148 will report the signal strength at RTIP and RRING in 2.5dB increments via RL3-RL0
located in the Receive Information Register 2. This feature is helpful when trouble shooting line
performance problems. See Table 5-2 for details.
Monitor applications in both E1 and T1 require various flat gain settings for the receive-side circuitry.
The DS2148 can be programmed to support these applications via the Monitor Mode control bits MM1
and MM0. When the monitor modes are enabled, the receiver will tolerate normal line loss up to –6dB.
See Table 4-4 for details.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| H3CWH-6436G | IDC CABLE - HKC64H/AE64G/HPL64H |
| 78M6618-PDU-1 | EVAL KIT DS8005 |
| RMM10DSEH | CONN EDGECARD 20POS .156 EYELET |
| M3TMK-1006R | IDC CABLE - MSD10K/MC10M/MCG10K |
| M3TFK-1618R | IDC CABLE - MSD16K/MC16M/MCF16K |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2148G | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2148G+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2148GB | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2148GN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2148GN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。