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參數(shù)資料
| 型號(hào)： | DS2148G+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 4/73頁(yè) |
| 文件大小： | 0K |
| 描述： | IC LIU E1/T1/J1 3.3V/5V 49-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 416 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | T1/E1/J1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 49-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 49-CSBGA（7x7） |
| 包裝： | 托盤(pán) |
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DS2148/DS21Q48
12 of 73
Table 2-3. Pin Descriptions in Parallel Port Mode (Sorted by Pin Name,
DS2148T)
NAME
PIN
I/O
FUNCTION
A0
to
A4
11
to
7
I
Address Bus. In nonmultiplexed bus operation (BIS1 = 0, BIS0 = 1),
serves as the address bus. In multiplexed bus operation (BIS1 = 0, BIS0 =
0), these pins are not used and should be tied low.
ALE(AS)
4
I
Address Latch Enable (Address Strobe). When using the parallel port
(BIS1 = 0) in multiplexed bus mode (BIS0 = 0), serves to demultiplex the
bus on a positive-going edge. In nonmultiplexed bus mode (BIS0 = 1),
should be tied low.
BIS0/BIS1
32/33
I
Bus Interface Select Bits 0 & 1. Used to select bus interface option. See
Table 2-1 for details.
BPCLK
31
O
Backplane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz
clock output that is referenced to RCLK selectable via CCR5.7 and
CCR5.6. In hardware mode, defaults to 16.384MHz output.
CS
1
I
Active-Low Chip Select. Must be low to read or write to the device.
D0/AD0
to
D7/AD7
19
to
12
I/O
Data Bus/Address/Data Bus. In non-multiplexed bus operation (BIS1 =
0, BIS0 = 1), serves as the data bus. In multiplexed bus operation (BIS1 =
0, BIS0 = 0), serves as an 8-bit multiplexed address/data bus.
HRST
29
I
Active-Low Hardware Reset. Bringing
HRST low will reset the DS2148
setting all control bits to their default state of all zeros.
INT
23
O
Active-Low Interrupt. Flags host controller during conditions and
change of conditions defined in the Status Register. Active low, open
drain output.
MCLK
30
I
Master Clock. A 2.048MHz (±50ppm) clock source with TTL levels is
applied at this pin. This clock is used internally for both clock/data
recovery and for jitter attenuation. Use of a T1 1.544MHz clock source is
optional.
See Note 1 on clock accuracy at the end of this table.
NA
-
I
Not Assigned. Should be tied low.
PBEO
24
O
PRBS Bit Error Output. The receiver will constantly search for a 215-1 or
a 220-1 PRBS depending on the ETS bit setting (CCR1.7). Remains high if
out of synchronization with the PRBS pattern. Goes low when
synchronized to the PRBS pattern. Any errors in the received pattern after
synchronization will cause a positive going pulse (with same period as E1
or T1 clock) synchronous with RCLK. PRBS bit errors can also be
reported to the ECR1 and ECR2 registers by setting CCR6.2 to a logic 1.
PBTS
44
I
Parallel Bus Type Select. When using the parallel port (BIS1 = 0), set
high to select Motorola bus timing, set low to select Intel bus timing. This
pin controls the function of the
RD(DS), ALE(AS), and WR(R/W) pins. If
PBTS = 1 and BIS1 = 0, then these pins assume the Motorola function
listed in parenthesis (). In serial port mode, this pin should be tied low.
RCLK
40
O
Receive Clock. Buffered recovered clock from the line. Synchronous to
MCLK in absence of signal at RTIP and RRING.
RD(DS)
2
I
Active-Low Read Input (Data Strobe). DS is active low when in
nonmultiplexed, Motorola mode. See the bus timing diagrams in Section
RCL/LOTC
25
O
Receive Carrier Loss/Loss of Transmit Clock. An output which will
toggle high during a receive carrier loss (CCR2.7 = 0) or will toggle high
if the TCLK pin has not been toggled for 5
s ±2s (CCR2.7 = 1). CCR2.7
defaults to logic 0 when in hardware mode.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2148G+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2148GB | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2148GN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2148GN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2148GNB | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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