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參數(shù)資料
| 型號： | DS2152LN |
| 英文描述： | Enhanced T1 Single-Chip Transceiver |
| 中文描述： | 增強型T1單芯片收發(fā)器 |
| 文件頁數(shù)： | 13/94頁 |
| 文件大?。?/td> | 1003K |
| 代理商： | DS2152LN |
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DS2152
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Write Input [
WR
] (Read/Write [R/
W
]).
WR
is an active low signal.
LINE INTERFACE PINS
Master Clock Input [MCLK].
A 1.544 MHz (± 50 ppm) clock source with TTL levels is applied at this
pin. This clock is used internally for both clock/data recovery and for jitter attenuation. A quartz crystal
of 1.544 MHz may be applied across MCLK and XTALD instead of the TTL level clock source.
Quartz Crystal Driver [XTALD].
A quartz crystal of 1.544 MHz may be applied across MCLK and
XTALD instead of a TTL level clock source at MCLK. Leave open circuited if a TTL clock source is
applied at MCLK.
Eight Times Clock [8XCLK]
. A 12.352 MHz clock that is frequency locked to the 1.544 MHz clock
provided from the clock/data recovery block (if the jitter attenuator is enabled on the receive side) or from
the TCLKI pin (if the jitter attenuator is enabled on the transmit side). Can be internally disabled via the
TEST2 register if not needed.
Line Interface Connect [LIUC].
Tie low to separate the line interface circuitry from the
framer/formatter circuitry and activate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. Tie high
to connect the line interface circuitry to the framer/formatter circuitry and deactivate the
TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI
pins.
TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins should be tied low.
When
LIUC
is
tied
high,
the
Receive Tip and Ring
[
RTIP & RRING].
Analog inputs for clock recovery circuitry. These pins
connect via a 1:1 transformer to the T1 line. See Section 14 for details.
Transmit Tip and Ring [TTIP & TRING].
Analog line driver outputs. These pins connect via a 1:1.15
or 1:1.36 step-up transformer to the T1 line. See Section 14 for details.
Receive Analog Positive Supply [RVDD].
5.0 volts ± 5%. Should be tied to the DVDD and TVDD pins.
Transmit Analog Positive Supply [TVDD].
5.0 volts ± 5%. Should be tied to the RVDD and DVDD
pins.
Digital Signal Ground [DVSS].
Should be tied to the RVSS and TVSS pins.
Receive Analog Signal Ground [RVSS].
0.0 volts. Should be tied to the DVSS and TVSS pins.
Transmit Analog Ground [TVSS].
0.0 volts. Should be tied to the RVSS and DVSS pins.
SUPPLY PINS
Digital Positive Supply [DVDD].
5.0 volts ± 5%. Should be tied to the RVDD and TVDD pins.
DS2152 REGISTER MAP
Table 1-3
ADDRESS
R/W
00
R/W
01
R/W
02
R/W
03
R/W
04
R/W
REGISTER NAME
FDL Control
FDL Status
FDL Interrupt Mask
Receive Performance Report Message
Receive Bit Oriented Code
REGISTER ABBREVIATION
FDLC
FDLS
FIMR
RPRM
RBOC
相關PDF資料 |
PDF描述 |
|---|---|
| DS2152L | Enhanced T1 Single-Chip Transceiver |
| DS2152 | Enhanced T1 Single-Chip Transceiver |
| DS2160Q | Data Encryption Processor |
| DS2160QN | Peripheral IC |
| DS2165QL | Solid-State Recorder |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS2152LN+ | 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2153DK | 功能描述:KIT DESIGN TXRX E1 DS2153 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標準包裝:1 系列:- 傳感器類型:CMOS 成像，彩色（RGB） 傳感范圍:WVGA 接口:I²C 靈敏度:60 fps 電源電壓:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相關產(chǎn)品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
| DS2153Q | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:E1 Single-Chip Transceiver |
| DS2153Q-A5 | 功能描述:IC TXRX E1 1-CHIP 5V 44-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標準包裝:750 系列:* |
| DS2153Q-A5/T&R | 制造商:Maxim Integrated Products 功能描述:IC TXRX E1 1-CHIP 5V 44-PLCC |
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