參數(shù)資料
型號： DS21554L+
廠商： Maxim Integrated Products
文件頁數(shù)： 121/124頁
文件大?。?/td> 0K
描述： IC TXRX E1 1-CHIP 5V 100-LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 90
功能： 單芯片收發(fā)器
接口： E1，HDLC，J1，T1
電路數(shù)： 1
電源電壓： 4.75 V ~ 5.25 V
電流 - 電源： 75mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤
包括： 遠程和 AIS 警報檢測器 / 發(fā)生器
產(chǎn)品目錄頁面： 1430 (CN2011-ZH PDF)
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
96 of 124
rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the
identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into
the instruction register’s parallel output. The ID code will always have a one in the LSB position. The
next 11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16
bits for the device and 4 bits for the version. See Table 16-2. Table 16-3 lists the device ID codes for the
SCT devices.
Table 16-2. ID Code Structure
MSB
LSB
Version
Contact Factory
Device ID
JEDEC
1
4 bits
16 bits
00010100001
1
Table 16-3. Device ID Codes
DEVICE
16-BIT ID
DS21354
0005h
DS21554
0003h
DS21352
0004h
DS21552
0002h
16.2.
Test Registers
IEEE 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register.
An optional test register has been included with the DS21354/554 design. This test register is the
identification register and is used in conjunction with the IDCODE instruction and the Test-Logic-Reset
state of the TAP controller.
Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and
digital I/O cells and is n bits in length. See Table 16-4 for all the cell bit locations and definitions.
Bypass Register
This is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ
instructions that provides a short path between JTDI and JTDO.
Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register
is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.
See Table 16-3 and Table 16-4 for more information on bit usage.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21554L+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21554LB 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21554LB+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21554LBN 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21554LBN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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