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| 型號(hào)： | DS2155LN |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 175/238頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX T1/E1/J1 1-CHIP 100-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS |
| 產(chǎn)品變化通告： | Product Discontinuation 20/Feb/2012 |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 功能： | 單芯片收發(fā)器 |
| 接口： | E1，HDLC，J1，T1 |
| 電路數(shù)： | 1 |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 電流 - 電源： | 75mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 管件 |
| 包括： | BERT 發(fā)生器和檢測(cè)器，CMI 編碼器和解碼器，HDLC 控制器 |
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DS2155
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6.2 Interrupt Handling
Various alarms, conditions, and events in the DS2155 can cause interrupts. For simplicity, these are all
referred to as events in this explanation. All status registers can be programmed to produce interrupts.
Each status register has an associated interrupt mask register. For example, SR1 (status register 1) has an
interrupt control register called IMR1 (interrupt mask register 1). Status registers are the only sources of
interrupts in the DS2155. On power-up, all writeable registers are automatically cleared. Since bits in the
IMRx registers have to be set = 1 to allow a particular event to cause an interrupt, no interrupts can occur
until the host selects which events are to product interrupts. Since there are potentially many sources of
interrupts on the DS2155, several features are available to help sort out and identify which event is
causing an interrupt. When an interrupt occurs, the host should first read the IIR1 and IIR2 registers
(interrupt information registers) to identify which status register (or registers) is producing the interrupt.
Once that is determined, the individual status register or registers can be examined to determine the exact
source. In multiple port configurations, two to eight DS2155s can be connected together by the 3-wire
ESIB feature. This allows multiple DS2155s to be interrogated by a single CPU port read cycle. The host
can determine the synchronization status, or interrupt status of up to eight devices with a single read. The
ESIB feature also allows the user to select from various events to be examined through this method. For
more information, see Section 29.
Once an interrupt has occurred, the interrupt handler routine should set the INTDIS bit (CCR3.6) to stop
further activity on the interrupt pin. After all interrupts have been determined and processed, the interrupt
hander routine should re-enable interrupts by setting the INTDIS bit = 0.
6.3 Status Registers
When a particular event or condition has occurred (or is still occurring in the case of conditions), the
appropriate bit in a status register is set to a 1. All of the status registers operate in a latched fashion. This
means that if an event or condition occurs a bit is set to a 1. It remains set until the user reads that bit. An
event bit is cleared when it is read and it is not set again until the event has occurred again. Condition bits
such as RBL, RLOS, etc., remain set if the alarm is still present.
The user always proceeds a read of any of the status registers with a write. The byte written to the register
informs the DS2155 which bits the user wishes to read and have cleared. The user writes a byte to one of
these registers, with a 1 in the bit positions the user wishes to read and a 0 in the bit positions the user
does not wish to obtain the latest information on. When a 1 is written to a bit location, the read register is
updated with the latest information. When a 0 is written to a bit position, the read register is not updated
and the previous value is held. A write to the status registers is immediately followed by a read of the
same register. This write-read scheme allows an external microcontroller or microprocessor to
individually poll certain bits without disturbing the other bits in the register. This operation is key in
controlling the DS2155 with higher order languages.
Status register bits are divided into two groups, condition bits and event bits. Condition bits are typically
network conditions such as loss-of-sync or all-ones detect. Event bits are typically markers such as the
one-second timer, elastic store slip, etc. Each status register bit is labeled as a condition or event bit.
Some of the status registers have bits for both the detection of a condition and the clearance of the
condition. For example, SR2 has a bit that is set when the device goes into a loss-of-sync state (SR2.0, a
condition bit) and a bit that is set (SR2.4, an event bit) when the loss-of-sync condition clears (goes in
sync). Some of the status register bits (condition bits) do not have a separate bit for the “condition clear”
event but rather the status bit can produce interrupts on both edges, setting and clearing. These bits are
marked as double interrupt bits. An interrupt is produced when the condition occurs and when it clears.
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| DS2156LN+ | IC TXRX T1/E1/J1 1-CHIP 100-LQFP |
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| DS2174QN+ | IC BERT ENHANCED 44-PLCC |
| DS2175SN+ | IC ELASTIC STORE T1/CEPT 16-SOIC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2155LN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1/E1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2155LNB | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2155LNB+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1/E1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2155LNC2+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1/E1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2156 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:T1/E1/J1 Single-Chip Transceiver |
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