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參數(shù)資料
| 型號： | DS2165-DS2165Q |
| 英文描述： | 16/24/32kbps ADPCM Processor |
| 中文描述： | 16/24/32kbps差分PcM處理器 |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 336K |
| 代理商： | DS2165-DS2165Q |
DS2165Q
3 of 17
CONTROL REGISTER
The control register establishes idle, algorithm reset, bypass, data format, and channel coding for the
selected channel.
The X-side and Y-side PCM interfaces can be independently disabled (output tri-stated) by IPD. When
IPD is set for both channels, the device enters a low-power standby mode. In this mode, the serial port
must not be operated faster than 39kHz.
ALRST resets the algorithm coefficients for the selected channel to their initial values. ALRST is cleared
by the device when the algorithm reset is complete.
Table 1. PIN DESCRIPTION
PIN
SYMBOL
TYPE
FUNCTION
2
RST
I
Reset.
A high-low-high transition resets the algorithm. The device should be
reset on power-up and when changing to or from the hardware mode.
3
4
6
7
8
9
TM0
TM1
A0
A1
A2
A3
A4
A5
I
Test Modes 0 and 1.
Connect to V
SS
for normal operation.
10
11
I
Address Select.
A0 = LSB, A5 = MSB. Must match address/command word
to enable the serial port.
12
SPS
I
Serial Port Select.
Connect to V
DD
to select the serial port; connect to V
SS
to
select the hardware mode.
Master Clock.
10MHz clock for the ADPCM processing engine; may be
asynchronous to SCLK, CLKX, and CLKY.
Signal Ground.
0V
X Data In.
Sampled on falling edge of CLKX during selected time slots.
X Data Clock.
Data clock for the X-side PCM interface; must be
synchronous with FSX.
X Frame Sync.
8kHz frame sync for the X-side PCM interface.
X Data Output.
Updated on rising edge of CLKX during selected time slots.
Serial Data Clock.
Used to write to the serial port registers.
Serial Data In.
Data for on-board control registers; sampled on the rising
edge of SCLK. LSB sent first.
Chip Select.
Must be low to write to the serial port.
13
MCLK
I
14
16
VSS
XIN
—
I
17
CLKX
I
18
20
21
FSX
XOUT
SCLK
I
O
I
22
SDI
I
23
CS
I
24
25
YOUT
FSY
O
I
Y Data Output.
Updated on rising edge of CLKY during selected time slots.
Y Frame Sync.
8kHz frame sync for the Y-side PCM interface.
Y Data Clock.
Data clock for the Y-side PCM interface; must be
synchronous with FSY.
Y Data In.
Sampled on falling edge of CLKY during selected time slots.
Positive Supply.
5.0V (3.0V for DS2165QL)
26
CLKY
I
27
28
YIN
VDD
I
—
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2165N | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS2165Q | 功能描述:音頻 DSP 16/24/32kbps ADPCM Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| DS2165Q/T&R | 制造商:Maxim Integrated Products 功能描述:ADPCM PROCESSOR, 16/24/32KB PLCC - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC PROC ADPCM 16/24/32K 28-PLCC 制造商:Maxim Integrated Products 功能描述:Audio DSPs 16/24/32kbps ADPCM Processor |
| DS2165Q/T&R+ | 制造商:Maxim Integrated Products 功能描述:ADPCM PROCESSOR 32KBPS PLCC T&R LF - Tape and Reel |
| DS2165Q/T&R | 功能描述:音頻 DSP 16/24/32kbps ADPCM Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
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