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參數(shù)資料
| 型號： | DS2172T+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 17/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TESTER BIT ERROR RATE 32-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 功能： | 位誤碼率測試器（BERT） |
| 接口： | T1 |
| 電路數(shù)： | 1 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電流 - 電源： | 10mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 包括： | 錯誤計數(shù)器，樣式發(fā)生器和檢測器 |
DS2172
4 of 22
DETAILED PIN DESCRIPTION Table 1
PIN
SYMBOL
TYPE
DESCRIPTION
1TL
I
Transmit Load. A positive-going edge loads the pattern generator with
the contents of the Pattern Set Registers. The MSB of the repetitive or
pseudorandom pattern appears at TDATA after the third positive edge of
TCLK from asserting TL. TL is logically OR’ed with PCR.7 and should
be tied to VSS if not used. See Figure 8 for timing information.
2
AD0
I/O
Data Bus. An 8-bit multiplexed address/data bus.
3
AD1
I/O
Data Bus. An 8-bit multiplexed address/data bus.
4
TEST
I
Test. Set high to 3-state all output pins ( INT , ADx, TDATA, RLOS).
Should be tied to VSS to enable all outputs.
5VSS
-
Signal Ground. 0.0V. Should be tied to local ground plane.
6
AD2
I/O
Data Bus. An 8-bit multiplexed address/data bus.
7
AD3
I/O
Data Bus. An 8-bit multiplexed address/data bus.
8
AD4
I/O
Data Bus. An 8-bit multiplexed address/data bus.
9
AD5
I/O
Data Bus. An 8-bit multiplexed address/data bus.
10
AD6
I/O
Data Bus. An 8-bit multiplexed address/data bus.
11
AD7
I/O
Data Bus. An 8-bit multiplexed address/data bus.
12
VSS
-
Signal Ground. 0.0V. Should be tied to local ground plane.
13
VDD
-
Positive Supply. 5.0V.
14
BTS
I
Bus Type Select. Strap high to select Motorola bus timing; strap low to
select Intel bus timing. This pin controls the function of the RD (DS),
ALE(AS), and WR (R/ W ) pins. If BTS = 1, then these pins assume the
function listed in parenthesis ().
15
RD
(DS)
I
Read Input (Data Strobe).
16
CS
I
Chip Select. Must be low to read or write the port.
17
ALE(AS)
I
Address Latch Enable (Address Strobe). A positive going edge serves
to demultiplex the bus.
18
WR
(R/ W )
I
Write Input (Read/Write).
19
INT
O
Alarm Interrupt. Flags host controller during conditions defined in
Status Register. Active low, open drain output.
20
VDD
-
Positive Supply. 5.0V.
21
VSS
-
Signal Ground. 0.0V. Should be tied to local ground plane.
22
LC
I
Load Count. A positive-going edge latches the current bit and bit error
count into the user accessible BCR and BECR registers and clears the
internal count registers. LC is logically OR’ed with control bit PCR.4.
Should be tied to VSS if not used.
23
RLOS
O
Receive Loss Of Sync. Indicates the real time status of the receive
synchronizer. Active high output.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2174 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:EBERT |
| DS2174DK | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced Bit Error-Rate Tester Design Kit |
| DS2174Q | 功能描述:電信集成電路 Enhanced Bit Error Rate Tester (BERT) RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
| DS2174Q/T&R+ | 制造商:Maxim Integrated Products 功能描述:BIT ERROR RATE TESTER 44PLCC - Tape and Reel |
| DS2174Q/T&R | 功能描述:電信集成電路 RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
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