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參數(shù)資料
| 型號(hào)： | DS2172T/T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 4/22頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TESTER BIT ERROR RATE 32-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS |
| 產(chǎn)品變化通告： | Product Discontinuation 20/Feb/2012 |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 功能： | 位誤碼率測(cè)試器（BERT） |
| 接口： | T1 |
| 電路數(shù)： | 1 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電流 - 電源： | 10mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 包括： | 錯(cuò)誤計(jì)數(shù)器，樣式發(fā)生器和檢測(cè)器 |
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DS2172
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10.0 PATTERN RECEIVE REGISTERS
The Pattern Receive Register (PRR) provides access to the data patterns received at RDATA. The
operation of these registers depends on the synchronization status of the DS2172. Asserting the RL bit
(PCR.3) or pin during an out-of -sync condition (SR.0 = 0) will latch the previous 32 bits of data received
at RDATA into the PRR registers. When the DS2172 is in sync (SR.0 = 1) asserting RL will latch the
pattern that to which the device has established synchronization. Since the receiver has no knowledge of
the start or end of the pattern, the data in the PRR registers will have no particular alignment. As an
example, if the receiver has synchronized to the pattern 00100110, PRR1 may report 10011000,
11000100 or any rotation thereof. Once synchronization is established, bit errors cannot be viewed in the
PRR registers.
PATTERN RECEIVE REGISTERS
(MSB)
(LSB)
PR31
PR30
PR29
PR28
PR27
PR26
PR25
PR24
PRR3 (addr.=10 Hex)
PR23
PR22
PR21
PR20
PR19
PR18
PR17
PR16
PRR2 (addr.=11 Hex)
PR15
PR14
PR13
PR12
PR11
PR10
PR9
PR8
PRR1 (addr.=12 Hex)
PR7
PR6
PR5
PR4
PR3
PR2
PR1
PR0
PRR0 (addr.=13 Hex)
11.0 STATUS REGISTER AND INTERRUPT MASK REGISTER
The Status Register (SR) contains information on the current real time status of the DS2172. When a
particular event has occurred, the appropriate bit in the register will be set to a 1. All of the bits in these
registers (except for the SYNC bit) operate in a latched fashion. This means that if an event occurs and a
bit is set to a 1 in any of the registers, it will remain set until the user reads that bit. For the BED, BCOF,
and BECOF status bits, they will be cleared when read and will not be set again until the event has
occurred again. For RLOS, RA0, and RA1 status bits, they will be cleared when read if the condition no
longer persists.
The SR register has the unique ability to initiate a hardware interrupt via the INT pin. Each of the alarms
and events in the SR can be either masked or unmasked from the interrupt pins via the Interrupt Mask
Register (IMR).
相關(guān)PDF資料 |
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| DS2174QN+ | IC BERT ENHANCED 44-PLCC |
| DS2175SN+ | IC ELASTIC STORE T1/CEPT 16-SOIC |
| DS2176QN | IC BUFFER RECEIVE T1 IND 28-PLCC |
| DS2180AQN+T&R | IC TRANSCEIVER T1 44-PLCC |
| DS2181AQN+ | IC TXRX CEPT PRIMARY RATE 44PLCC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2174 | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:EBERT |
| DS2174DK | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Enhanced Bit Error-Rate Tester Design Kit |
| DS2174Q | 功能描述:電信集成電路 Enhanced Bit Error Rate Tester (BERT) RoHS:否 制造商:STMicroelectronics 類(lèi)型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
| DS2174Q/T&R+ | 制造商:Maxim Integrated Products 功能描述:BIT ERROR RATE TESTER 44PLCC - Tape and Reel |
| DS2174Q/T&R | 功能描述:電信集成電路 RoHS:否 制造商:STMicroelectronics 類(lèi)型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
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