參數(shù)資料
型號: DS2175
英文描述: T1/CEPT Elastic Store
中文描述: T1/CEPT彈性存儲器
文件頁數(shù): 3/12頁
文件大?。?/td> 243K
代理商: DS2175
DS2175
3 of 12
PIN Description Table 1
DESCRIPTION
Receive Clock Select
. Tie to V
SS
for 1.544 MHz applications, to
V
DD
for 2.048 MHz.
Receive Clock
. 1.544 or 2.048 MHz data clock.
Receive Serial Data
. Sampled on falling edge of RCLK.
Receive Multifram Sync
. Rising edge establishes receive side
frame and multiframe boundaries.
Frame Slip Directions
. State indicates direction of last slip;
latched on slip occurrence.
Frame Slip
. Active low, open collector output. Held low for 65
SYSCLK cycles when a slip occurs.
Align
. Recenters buffer on next system side frame boundary when
forced low; negative edge-triggered.
Signal Ground
. 0.0 volts.
System Clock Select
. Tie to V
SS
for 1.544 MHz applications, to
V
DD
for 2.048 MHz.
Serial/Parallel Select
. Tie to V
SS
for parallel backplane
applications, to V
DD
for serial.
System Channel Clock
. Transitions high on channel boundaries;
useful for serial to parallel conversion of channel data.
System Frame Sync
. Rising edge establishes system side frame
boundaries.
System Multiframe Sync
. Slip-compensated multiframe output;
used with RMSYNC to monitor depth of store real time.
System Serial Data
. Updated on rising edge of SYSCLK.
System Clock
. 1.544 or 2.048 MHz data clock.
Positive Supply
. 5.0 volts.
PIN
1
SYMBOL
RCLKSEL
TYPE
I
2
3
4
RCLK
RSER
RMSYNC
I
I
I
5
FSD
O
6
SLIP
O
7
ALN
I
8
9
V
SS
SCLKSEL
I
10
S/
P
I
11
SCHCLK
O
12
SFSYNC
I
13
SMSYNC
O
14
15
16
SSER
SYSCLK
V
DD
O
I
PCM BUFFER
The DS2175 utilizes a 2–frame buffer to synchronize in-coming PCM data to the system backplane clock.
Buffer depth is mode–dependent; 2.048 MHz to 2.048 MHz applications utilize 64 bytes of buffer
memory, while all other modes are supported by 48 bytes. The buffer samples data at RSER on the falling
edge of RCLK. Output data appears at SSER and is updated on the rising edge of SYSCLK. The buffer
depth is constantly monitored by onboard contention logic; a “slip” occurs when the buffer is completely
emptied or filled. Slips automatically recenter the buffer to a one–frame depth and always occur on frame
boundaries.
DATA FORMAT
Data is presented to, and output from, the elastic store in a “framed” format. A rising edge at RMSYNC
and SFSYNC establishes frame boundaries for the receive and system sides. North American (T1) frames
contain 24 data channels of 8 bits each and an F–bit (193 bits total). European (CEPT) frames contain 32
data channels (256 bits). The frame rate of both systems is 8 KHz. RMSYNC and SFSYNC do not
require a pulse at every frame boundary; if desired, they may be pulsed once to establish frame alignment.
Internal counters will then maintain the frame alignment and may be reinforced by the next rising edge at
RMSYNC and/or SFSYNC.
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS2175+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1/CEPT Elastic Store RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2175N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1/CEPT Elastic Store RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2175S 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2175S/T&R 制造商:Maxim Integrated Products 功能描述:ELASTIC STORE-SOIC-TRL - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC ELASTIC STORE T1/CEPT 16-SOIC 制造商:Maxim Integrated Products 功能描述:Network Controller & Processor ICs T1/CEPT Elastic Store
DS2175S/T&R 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1/CEPT Elastic Store RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray