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參數(shù)資料
| 型號(hào)： | DS2176 |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | Digital Transmission Support |
| 英文描述： | DATACOM, ELASTIC BUFFER, PDIP24 |
| 封裝： | 0.300 INCH, DIP-24 |
| 文件頁(yè)數(shù)： | 9/15頁(yè) |
| 文件大?。?/td> | 294K |
| 代理商： | DS2176 |
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DS2176
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PIN DESCRIPTION Table 1
PIN
SYMBOL
TYPE
DESCRIPTION
1
SIGN
I
Signaling Inhibit. When low, ABCD signaling updates are disabled for
a period determined by SM0 and SM1, or until returned high.
2
RMSYNC
I
Receive Multifram Sync. Must be pulsed high at multiframe
boundaries to establish frame and multiframe alignment.
3
RCLK
I
Receive Clock. Primary 1.544 MHz clock.
4
RSER
I
Receive Serial Data. Sampled on Falling edge of RCLK.
5
6
7
8
A
B
C
D
O
Robbed-Bit Signaling Outputs.
9
SCHCLK
O
System Channel Clock. Transitions high on channel boundaries; useful
for serial to parallel conversion of channel data.
10
11
SM0
SM1
I
Signaling Modes 0 and 1. Select signaling supervision technique.
12
VSS
–
Signal Ground. 0.0 volts.
13
S/ P
I
Serial/Parallel Select. Tie to VSS for parallel backplane applications, to
VDD for serial.
14
FMS
I
Frame Mode Select. Tie to VSS to select 193S(D4) framing to VDD for
193E (extended).
15
ALN
I
Align. Recenters buffer on next system side frame boundary when
forced low.
16
SFSYNC
I
System Frame Sync. Rising edge establishes start of frame.
17
SIGFRZ
O
Signaling Freeze. When high, indicates signaling updates have been
disabled internally via a slip or externally by forcing SIGH low.
18
SMSYNC
O
System Multiframe Sync. Slip-compensated multiframe output;
indicates when signaling updates are made.
19
SBIT8
O
System Bit 8. High during the LSB time of each channel. Used to
reinsert extracted signaling into outgoing data stream.
20
SLIP
O
Frame Slip. Active low, open collector output. Held low for 65
SYSCLK cycles when a slip occurs.
21
SSER
O
System Serial Out. Updated on rising edge of SYSCLK.
22
SYSCLK
I
System Clock. 1.544 or 2.048 MHz data clock.
23
SCLKSEL
I
System Clock Select. Tie to VSS for 1.544 MHz applications, to VDD for
2.048 MHz.
24
VDD
–
Positive Supply. 5.0 volts.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2176Q | DATACOM, ELASTIC BUFFER, PQCC28 |
| DS2180AQ | DATACOM, FRAMER, PQCC44 |
| DS2180AQN | DATACOM, FRAMER, PQCC44 |
| DS2180A | DATACOM, FRAMER, PDIP40 |
| DS2180AN | DATACOM, FRAMER, PDIP40 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2176+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Receive Buffer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2176IND | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| DS2176N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Receive Buffer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2176Q | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Receive Buffer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2176Q/T&R | 制造商:Maxim Integrated Products 功能描述:T1 ELASTIC STORE PLCC TRL - Tape and Reel 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:IC BUFFER RECEIVE T1 28-PLCC |
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