參數(shù)資料
型號(hào): DS2176QN
廠商: Maxim Integrated Products
文件頁數(shù): 11/15頁
文件大?。?/td> 0K
描述: IC BUFFER RECEIVE T1 IND 28-PLCC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 37
類型: 緩沖器
Tx/Rx類型: T1
延遲時(shí)間: 100ns
電容 - 輸入: 5pF
電源電壓: 4.5 V ~ 5.5 V
電流 - 電源: 10mA
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 28-PLCC(11.51x11.51)
包裝: 管件
DS2176
5 of 15
passed through the receive buffer and presented at SSER immediately after the rising edge of the system
side frame sync. The F–bit is dropped in 2.048 MHz applications and the MSB of channel 1 appears at
SSER one bit period after a rising edge at SFSYNC. SSER is forced to 1 in all channels greater than 24.
See Figures 3 and 4.
In 2.048 MHz applications (SCLKSEL=1), the PCM buffer control logic establishes slip criteria different
from that used in 1.544 MHz applications to compensate for the faster system-side read frequency.
PARALLEL COMPATIBILITY
The DS2176 is compatible with parallel and serial back-planes. Channel 1 data appears at SSER after a
rising edge at SFSYNC as shown in Figures 3 and 4 (serial applications, S/ P =1). The device utilizes a
look–ahead circuit in parallel applications (S/ P =0). Data is output 8 clocks earlier, allowing the user to
convert parallel data eternally.
SYSTEM MULTIFRAME BOUNDARY TIMING (SYSCLK = 1.544 MHz) Figure 3
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