參數(shù)資料
型號(hào): DS2180AQ+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 23/35頁
文件大小: 0K
描述: IC TRANSCEIVER T1 44-PLCC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 500
功能: 收發(fā)器
接口: T1
電路數(shù): 1
電源電壓: 4.5 V ~ 5.5 V
電流 - 電源: 3mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 帶卷 (TR)
包括: 警報(bào)生成和檢測(cè),B7 填充模式,B8ZS 模式,錯(cuò)誤檢測(cè)和計(jì)數(shù)器,“硬件”模式,透明模式
DS2180A
3 of 35
TRANSMIT PIN DESCRIPTION (40-PIN DIP ONLY) Table 1
PIN
SYMBOL
TYPE
DESCRIPTION
1
TMSYNC
I
Transmit Multiframe Sync. May be pulsed high at multiframe boundaries to
reinforce multiframe alignment or tied low, which allows internal multiframe
counter to free run.
2
TFSYNC
I
Transmit Frame Sync. Rising edge identifies frame boundary; may be pulsed
every frame to reinforce internal frame counter or tied low (allowing TMSYNC to
establish frame and multiframe alignment).
3TCLK
I
Transmit Clock. 1.544 MHz primary clock.
4
TCHCLK
O
Transmit Channel Clock. 192 kHz clock which identifies time slot (channel)
boundaries. Useful for parallel-to-serial conversion of channel data.
5TSER
I
Transmit Serial Data. NRZ data input, sample on falling edge of TCLK.
6TMO
O
Transmit Multiframe Out. Output of internal multiframe counter indicates
multiframe boundaries. 50% duty cycle.
7TSIGSEL
O
Transmit Signaling Select. .667 kHz clock which identifies signaling frame A and
C in 193E framing. 1.33 kHz clock in 193S.
8TSIGFR
O
Transmit Signaling Frame. High during signaling frames, low otherwise.
9TABCD
I
Transmit ABCD Signaling. When enabled via TCR.4, sampled during channel
LSB time in signaling frames on falling edge of TCLK.
10
TLINK
I
Transmit Link Data. Sampled during the F-bit time (falling edge of TCLK) of odd
frames for insertion into the outgoing data stream (193E-FDL insertion). Sampled
during the F-bit time of even frames for insertion into the outgoing data (193S-
External S-Bit insertion).
11
TLCLK
O
Transmit Link Clock. 4 kHz demand clock for TLINK input.
12
13
TPOS
TNEG
O
Transmit Bipolar Data Outputs. Updated on rising edge of TCLK.
PORT PIN DESCRIPTION (40-PIN DIP ONLY) Table 2
PIN
SYMBOL
TYPE
DESCRIPTION
14
INT
1
O
Receive Alarm Interrupt.
Flags host controller during alarm conditions. Active
low, open drain output.
15
SDI
1
I
Serial Data In.
Data for onboard registers. Sampled on rising edge of SCLK.
16
SDO
1
O
Serial Data Out.
Control and status information from onboard registers. Updated
on falling edge of SCLK, tri-stated during serial port write or when CS is high.
17
CS
1
I
Chip Select.
Must be low to write or read the serial port registers.
18
SCLK
1
I
Serial Data Clock.
Used to write or read the serial port registers.
19
SPS
I
Serial Port Select.
Tie to VDD to select serial port. Tie to VSS to select hardware
mode.
NOTE:
1. Multifunction pins. See “Hardware Mode Description."
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