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| 型號(hào)： | DS21FF42 |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PBGA300 |
| 封裝： | 27 X 27 MM, BGA-300 |
| 文件頁(yè)數(shù)： | 76/115頁(yè) |
| 文件大?。?/td> | 534K |
| 代理商： | DS21FF42 |
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DS21FF42/DS21FT42
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enabled or disabled and vice versa. Also, each elastic store can interface to either a 1.544 MHz or 2.048
MHz backplane without regard to the backplane rate the other elastic store is interfacing.
Two mechanisms are available to the user for resetting the elastic stores. The Elastic Store Reset (TX -
CCR7.4 & RX - CCR7.5) function forces the elastic stores to a depth of one frame unconditionally. Data
is lost during the reset. The second method, the Elastic Store Align (TX - CCR6.5 & RX - CCR6.6)
forces the elastic store depth to a minimum depth of half a frame only if the current pointer separation is
already less then half a frame. If a realignment occurs data is lost. In both mechanisms, independent
resets are provided for both the receive and transmit elastic stores.
17.1 RECEIVE SIDE
If the receive side elastic store is enabled (CCR1.2=1), then the user must provide either a 1.544 MHz
(CCR1.3=0) or 2.048 MHz (CCR1.3=1) clock at the RSYSCLK pin. The user has the option of either
providing a frame/multiframe sync at the RSYNC pin (RCR2.3=1) or having the RSYNC pin provide a
pulse on frame boundaries (RCR2.3=0). If the user wishes to obtain pulses at the frame boundary, then
RCR2.4 must be set to zero and if the user wishes to have pulses occur at the multiframe boundary, then
RCR2.4 must be set to one. The framer will always indicate frame boundaries via the RFSYNC output
whether the elastic store is enabled or not. If the elastic store is enabled, then multiframe boundaries will
be indicated via the RMSYNC output. If the user selects to apply a 2.048 MHz clock to the RSYSCLK
pin, then the data output at RSER will be forced to all ones every fourth channel. Hence channels 1
(except for the MSB), 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be forced
to a one. The F–bit will be passed in the MSB of channel 1. Also, in 2.048 MHz applications, the
RCHBLK output will be forced high during the same channels as the RSER pin. See Section 23 for more
details. This is useful in T1 to CEPT (E1) conversion applications. If the 386–bit elastic buffer either
fills or empties, a controlled slip will occur. If the buffer empties, then a full frame of data (193 bits) will
be repeated at RSER and the SR1.4 and RIR1.3 bits will be set to a one. If the buffer fills, then a full
frame of data will be deleted and the SR1.4 and RIR1.4 bits will be set to a one.
17.2 TRANSMIT SIDE
The operation of the transmit elastic store is very similar to the receive side. The transmit side elastic
store is enabled via CCR1.7. A 1.544 MHz (CCR1.4=0) or 2.048 MHz (CCR1.4=1) clock can be applied
to the TSYSCLK input. If the user selects to apply a 2.048 MHz clock to the TSYSCLK pin, then the
data input at TSER will be ignored every fourth channel. Hence channels 1 (except for the MSB), 5, 9,
13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be ignored. A special case exists for
the MSB of channel 1. Via TCR1.6 the MSB of channel 1 can be sampled as the F-bit. The user must
supply a 8 kHz frame sync pulse to the TSSYNC input. Also, in 2.048 MHz applications, the TCHBLK
output will be forced high during the channels ignored by the framer. See Section 23 for more details.
Controlled slips in the transmit elastic store are reported in the RIR2.3 bit and the direction of the slip is
reported in the RIR2.5 and RIR2.4 bits.
17.3 MINIMUM DELAY SYNCHRONOUS RSYSCLK/TSYSCLK MODE
In applications where the framer is connected to backplanes that are frequency locked to the recovered T1
clock (i.e., the RCLK output), the full two frame depth of the onboard elastic stores is really not needed.
In fact, in some delay sensitive applications, the normal two frame depth may be excessive. Register bits
CCR3.7 and CCR3.0 control the RX and TX elastic stores depths.
In this mode, RSYSCLK and
TSYSCLK must be tied together and they must be frequency locked to RCLK. All of the slip contention
logic in the framer is disabled (since slips cannot occur). Also, since the buffer depth is no longer two
frames deep, the framer must be set up to source a frame pulse at the RSYNC pin and this output must be
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS21FF42N | DATACOM, FRAMER, PBGA300 |
| DS21FT44N | DATACOM, FRAMER, PBGA300 |
| DS21FT44 | DATACOM, FRAMER, PBGA300 |
| DS21Q352 | DATACOM, PCM TRANSCEIVER, PBGA256 |
| DS21Q354 | DATACOM, PCM TRANSCEIVER, PBGA256 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21FF42+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FF42N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FF42N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FF44 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FF44N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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