DS21FT40
6 of 87
TABLE OF CONTENTS
DESCRIPTION..........................................................................................................................................................................1
1.
DS21FT40 PIN DESCRIPTION.......................................................................................................................................8
2.
DS21FT44 PIN FUNCTION DESCRIPTION...............................................................................................................16
3.
DS21FT40 REGISTER MAP..........................................................................................................................................19
4.
PARALLEL PORT..........................................................................................................................................................24
5.
CONTROL, ID AND TEST REGISTERS.....................................................................................................................24
6.
STATUS AND INFORMATION REGISTERS............................................................................................................33
7.
ERROR COUNT REGISTERS......................................................................................................................................39
8.
DS0 MONITORING FUNCTION..................................................................................................................................41
9.
SIGNALING OPERATION............................................................................................................................................44
9.1
9.2
PROCESSOR BASED SIGNALING........................................................................................................................44
HARDWARE BASED SIGNALING........................................................................................................................47
10.
PER–CHANNEL CODE GENERATION AND LOOPBACK................................................................................47
10.1
TRANSMIT SIDE CODE GENERATION...............................................................................................................47
10.1.1
Simple Idle Code Insertion and Per–Channel Loopback...................................................................................47
10.1.2
Per–Channel Code Insertion .............................................................................................................................48
10.2
RECEIVE SIDE CODE GENERATION ..................................................................................................................49
11.
CLOCK BLOCKING REGISTERS ..........................................................................................................................50
12.
ELASTIC STORES OPERATION ............................................................................................................................50
12.1
12.2
RECEIVE SIDE.........................................................................................................................................................51
TRANSMIT SIDE.....................................................................................................................................................51
13.
ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION................................................................51
13.1
13.2
INTERNAL REGISTER SCHEME BASED ON DOUBLE–FRAME.....................................................................51
INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME................................................................53
14.
HDLC CONTROLLER FOR THE SA BITS OR DS0.............................................................................................55
14.1
14.2
14.3
14.4
G
ENERAL
O
VERVIEW
..................................................................................................................................................55
HDLC S
TATUS
R
EGISTERS
.........................................................................................................................................56
B
ASIC
O
PERATION
D
ETAILS
........................................................................................................................................57
HDLC R
EGISTER
D
ESCRIPTION
..................................................................................................................................58
15.
INTERLEAVED PCM BUS OPERATION ..............................................................................................................64
16.
TIMING DIAGRAMS.................................................................................................................................................67
17.
OPERATING PARAMETERS...................................................................................................................................75
18.
DS21FT40 MECHANICAL DIMENSIONS..............................................................................................................86