參數(shù)資料
型號: DS21FT40N
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA300
封裝: BGA-300
文件頁數(shù): 11/87頁
文件大小: 386K
代理商: DS21FT40N
DS21FT40
19 of 87
Signal Name:
CS1* TO CS3*
Signal Description:
Chip Select
Signal Type:
Input
Must be low to read or write to a specific DS21Q44 die. These are active low signals.
Signal Name:
WR* (R/W*)
Signal Description:
Write Input (Read/Write)
Signal Type:
Input
WR* is an active low signal.
TEST ACCESS PORT PINS
Signal Name:
TEST
Signal Description:
3–State Control
Signal Type:
Input
Set high to 3–state all output and I/O pins (including the parallel control port). Set low for normal
operation. Useful in board level testing.
SUPPLY PINS
Signal Name:
VDD
Signal Description:
Positive Supply
Signal Type:
Supply
2.97 to 3.63 volts.
Signal Name:
VSS
Signal Description:
Signal Ground
Signal Type:
Supply
0.0 volts.
3. DS21FT40 REGISTER MAP
Register Map for Each Quad Framer Sorted by Address Table 3-1
ADDRESS
R/W
REGISTER NAME
REGISTER
ABBREVIATION
00
R
BPV or Code Violation Count 1
VCR1
01
R
BPV or Code Violation Count 2
VCR2
02
R
CRC4 Error Count 1 / FAS Error Count 1
CRCCR1
03
R
CRC4 Error Count 2
CRCCR2
04
R
E-Bit Count 1 / FAS Error Count 2
EBCR1
05
R
E-Bit Count 2
EBCR2
06
R/W
Status 1
SR1
07
R/W
Status 2
SR2
08
R/W
Receive Information
RIR
09
R/W
Test 2
TEST2 (set to 00h)
0A
Not used
(set to 00H)
0B
Not used
(set to 00H)
0C
Not used
(set to 00H)
相關(guān)PDF資料
PDF描述
DS21FT40 DATACOM, FRAMER, PBGA300
DS21FT42 DATACOM, FRAMER, PBGA300
DS21FT42N DATACOM, FRAMER, PBGA300
DS21FF42 DATACOM, FRAMER, PBGA300
DS21FF42N DATACOM, FRAMER, PBGA300
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