參數(shù)資料
型號(hào): DS21FT42
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA300
封裝: 27 X 27 MM, BGA-300
文件頁數(shù): 27/115頁
文件大小: 534K
代理商: DS21FT42
DS21FF42/DS21FT42
19 of 115
DS21Q42 ENHANCED QUAD T1 FRAMER Figure 6-1
7. DS21Q42 PIN FUNCTION DESCRIPTION
This section describes the signals on the DS21Q42 die. Signals which are not bonded out or have limited
functionality in the DS21FT42 and DS21FF42 are noted in italics.
VSS
VDD
FRAMER #1
FRAMER #3
FRAMER #2
FRAMER #0
Parallel & Test Control Port
(routed to all blocks)
D0 to D7 /
AD0 to AD7
FS1
BTS
INT*
WR*
(R/W*)
RD*
(DS*)
FS0
CS*
TEST
ALE
(AS)/
A6
A0 to A5,
A7
MUX
7
8
FMS
F
ra
m
e
rLoop
bac
k
P
a
y
lo
ad
Loo
pbac
k
A
IS
G
ener
a
ti
o
n
B8
Z
S
En
c
o
d
e
CR
C
G
ener
a
ti
o
n
Y
e
llo
w
A
la
rm
G
ener
ati
o
n
S
ignal
ing
Ins
e
rt
io
n
Cl
e
a
rCha
n
e
l
FD
L
In
s
e
rt
io
n
F-
B
it
I
n
s
e
rt
io
n
Receive Side Framer
Transmit Side Formatter
BP
V
C
o
u
n
te
r
Al
a
rm
D
e
te
c
tio
n
P
e
r-
C
hannel
Code
Ins
e
rt
Elastic
Store
O
ne'
s
Dens
it
y
E
n
fo
rc
er
Loop
Co
de
G
e
ner
a
ti
o
n
O
ne'
s
D
ens
it
y
M
oni
tor
sync
data
clock
sync
data
clock
TSYNC
TCLK
TCHCLK
TSER
TCHBLK
RCHCLK
RCHBLK
RLCLK
RMSYNC
TSSYNC
TSYSCLK
RLINK
RSER
RSYSCLK
RSYNC
RFSYNC
TLINK
TLCLK
FDL Extraction
Timing Control
Elastic
Store
Sync Control
Timing Control
B8
Z
S
D
e
co
d
e
r
S
y
nc
h
roni
z
e
r
Loop
Co
de
De
tec
to
r
CR
C/F
ram
e
E
rr
o
r
C
o
u
n
t
S
ignal
in
g
E
x
tr
ac
ti
on
C
h
a
n
e
lMa
rk
in
g
Signaling
Buffer
RSIG
Hardware
Signaling
Insertion
TSIG
Remote
Lo
opbac
k
8MCLK
P
e
r-
Chann
el
C
ode
Ins
e
rt
P
e
r-
C
hannel
Loopb
a
c
k
64-Byte Buffer
BOM Detection
RPOS
RCLK
RNEG
TPOS
TNEG
CLKS I
FDL Insertion
64-Byte Buffer
BOM Generation
HDLC Engine
DS0 Insertion
HDLC Engine
DS0 Insertion
Power
3
JTAG Port
JTRST*
JTMS
JTCLK
JTDI
JTDO
RLOS/LOTC 1
1
Note:
1. Alternate pin functions. Consult data sheet for restrictions.
LOTC DET
&
MUX
8.192MHz Clock
Synthesizer
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DS21FT42N DATACOM, FRAMER, PBGA300
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