參數(shù)資料
型號(hào)： DS21Q348
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 11/76頁(yè)
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 QUAD 3.3V 144BGA
標(biāo)準(zhǔn)包裝： 90
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 144-BBGA
供應(yīng)商設(shè)備封裝： 144-PBGA（17x17）
包裝： 管件
DS21348/DS21Q348
19 of 76
NAME
PIN
I/O
FUNCTION
MCLK
30
I
Master Clock. A 2.048MHz (±50ppm) clock source with TTL
levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz
clock source is optional. G.703 requires an accuracy of
±50ppm for
both T1 and E1. TR62411 and ANSI specs require an accuracy of
±32ppm for T1 interfaces.
MM0/MM1
18/19
I
Monitor Mode Select Bits 0 and 1 [H/W Mode]. These inputs
determine if the receive equalizer is in a monitor mode (Table 2-11).
NA
—
I
Not Assigned. Should be tied low.
NRZE
3
I
NRZ Enable [H/W Mode]
0 = Bipolar data at RPOS/RNEG and TPOS/TNEG
1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a
positive going pulse when device receives a BPV, CV, or EXZ.
PBEO
24
O
PRBS Bit Error Output. The receiver will constantly search for a
QRSS (T1) or a 215-1 (E1) PRBS depending whether T1 or E1
mode is selected. Remains high if out of synchronization with the
PRBS pattern. Goes low when synchronized to the PRBS pattern.
Any errors in the received pattern after synchronization will cause a
positive going pulse (with same period as E1 or T1 clock)
synchronous with RCLK.
RCLK
40
O
Receive Clock. Buffered recovered clock from the line.
Synchronous to MCLK in absence of signal at RTIP and RRING.
RCL
25
O
Receive Carrier Loss. An output which will toggle high during a
receive carrier loss.
RNEG
39
O
Receive Negative Data. Updated on the rising edge (CES = 0) or
the falling edge (CES = 1) of RCLK with the bipolar data out of the
line interface. Set NRZE to a one for NRZ applications. In NRZ
mode, data will be output on RPOS while a received error will cause
a positive-going pulse synchronous with RCLK at RNEG. See
Section 6.4 for details.
RPOS
38
O
Receive Positive Data. Updated on the rising edge (CES = 0) or the
falling edge (CES = 1) of RCLK with bipolar data out of the line
interface. Set NRZE pin to a one for NRZ applications. In NRZ
mode, data will be output on RPOS while a received error will cause
a positive-going pulse synchronous with RCLK at RNEG. See
section 6.4 for details.
RT0/RT1
44/23
I
Receive LIU Termination Select Bits 0 and 1 [H/W Mode]. These
inputs determine the receive termination. See Table 2-12.
RTIP/
RRING
27/28
I
Receive Tip and Ring. Analog inputs for clock recovery circuitry.
These pins connect via a 1:1 transformer to the line. See Section 5
for details.
SCLKE
4
I
Receive and Transmit Synchronization Clock Enable
0 = disable 2.048MHz synchronization transmit and receive mode
1 = enable 2.048 Hz synchronization transmit and receive mode
TCLK
43
I
Transmit Clock. A 2.048MHz or 1.544MHz primary clock. Used to
clock data through the transmit side formatter.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21Q348B 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q348DK 功能描述:網(wǎng)絡(luò)開(kāi)發(fā)工具 RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V
DS21Q348N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q348NB 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q348-W 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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