參數(shù)資料
型號(hào): DS21Q42TN
廠(chǎng)商: DALLAS SEMICONDUCTOR
元件分類(lèi): Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP128
封裝: TQFP-128
文件頁(yè)數(shù): 95/119頁(yè)
文件大?。?/td> 1309K
代理商: DS21Q42TN
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DS21Q42
77 of 119
For all bus configurations, one framer will be configured as the master device and the remaining framers
on the shared bus will be configured as slave devices. Refer to the IBO register description below for
more detail. In the 4.096 MHz bus configuration there is one master and one slave per bus. Figure 18-1
shows the DS21Q42 configured to support two 4.096 MHz buses. Bus 1 consists of framers 0 and 1. Bus
2 consists of framers 2 and 3. Framers 0 and 2 are programmed as master devices. Framers 1 and 3 are
programmed as slave devices. In the 8.192 MHz bus configuration there is one master and three slaves.
Figure 18-2 shows the DS21Q42 configured to support a 8.192 MHz bus. Framers 0 is programmed as
the master device. Framers 1, 2 and 3 are programmed as slave devices. Consult timing diagrams in
section 20 for additional information.
When using the frame interleave mode, all framers that share an interleaved bus must have receive signals
(RPOS & RNEG) that are synchronous with each other. The received signals must originate from the
same clock reference. This restriction does not apply in the byte interleave mode.
IBO: INTERLEAVE BUS OPERATION REGISTER (Address = 94 Hex)
(MSB)
(LSB)
----
IBOEN
INTSEL
MSEL0
MSEL1
SYMBOL
POSITION
NAME AND DESCRIPTION
-IBO.6
Not Assigned. Should be set to 0.
-IBO.6
Not Assigned. Should be set to 0.
-IBO.5
Not Assigned. Should be set to 0.
-IBO.4
Not Assigned. Should be set to 0.
IBOEN
IBO.3
Interleave Bus Operation Enable
0 = Interleave Bus Operation disabled.
1 = Interleave Bus Operation enabled.
INTSEL
IBO.2
Interleave Type Select
0 = Byte interleave.
1 = Frame interleave.
MSEL0
IBO.1
Master Device Bus Select Bit 0 See table 18-1.
MSEL1
IBO.0
Master Device Bus Select Bit 1 See table 18-1.
Master Device Bus Select Table 18-1
MSEL1
MSEL0
Function
0
Slave device.
0
1
Master device with 1 slave device (4.096 MHz bus rate)
1
0
Master device with 3 slave devices (8.192 MHz bus rate)
11
Reserved
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