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參數(shù)資料
| 型號： | DS21Q42TN |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 72/116頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FRAMER ENHANCED T1 4X 128TQFP |
| 標(biāo)準(zhǔn)包裝： | 72 |
| 控制器類型： | T1 調(diào)幀器 |
| 接口： | 并行/串行 |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 電流 - 電源： | 75mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP（14x20） |
| 包裝： | 管件 |
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DS21Q42
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13.3 Minimum Delay Synchronous RSYSCLK/TSYSCLK Mode
In applications where the framer is connected to backplanes that are frequency locked to the recovered T1
clock (i.e., the RCLK output), the full two frame depth of the onboard elastic stores is really not needed.
In fact, in some delay sensitive applications, the normal two frame depth may be excessive. Register bits
CCR3.7 and CCR3.0 control the RX and TX elastic stores depths. In this mode, RSYSCLK and
TSYSCLK must be tied together and they must be frequency locked to RCLK. All of the slip contention
logic in the framer is disabled (since slips cannot occur). Also, since the buffer depth is no longer two
frames deep, the framer must be set up to source a frame pulse at the RSYNC pin and this output must be
tied to the TSSYNC input. On power–up after the RSYSCLK and TSYSCLK signals have locked to the
RCLK signal, the elastic stores should be reset.
14.
HDLC CONTROLLER
The DS21Q42 has an enhanced HDLC controller configurable for use with the Facilities Data Link or
DS0s. There are 64 byte buffers in both the transmit and receive paths. The user can select any DS0 or
multiple DS0s as well as any specific bits within the DS0(s) to pass through the HDLC controller. See
Figure 20-15 for details on formatting the transmit side. Note that TBOC.6 = 1 and TDC1.7 = 1 cannot
exist without corrupting the data in the FDL. For use with the FDL, see section 15.1. See Table 14-1 for
configuring the transmit HDLC controller.
Four new registers were added for the enhanced functionality of the HDLC controller; RDC1, RDC2,
TDC1, and TDC2. Note that the BOC controller is functional when the HDLC controller is used for
DS0s. Section 15 contains all of the HDLC and BOC registers and information on FDL/Fs Extraction
and Insertion with and without the HDLC controller.
Table 14-1. TRANSMIT HDLC CONFIGURATION
FUNCTION
TBOC.6
TDC1.7
TCR1.2
DS0(s)
0
1
1 or 0
FDL
1
0
1
Disable
0
1 or 0
14.1 HDLC for DS0s
When using the HDLC controllers for DS0s, the same registers shown in section 15 will be used except
for the TBOC and RBOC registers and bits HCR.7, HSR.7, and HIMR.7. As a basic guideline for
interpreting and sending HDLC messages and BOC messages, the following sequences can be applied.
Receive a HDLC Message
1) Enable RPS interrupts.
2) Wait for interrupt to occur.
3) Disable RPS interrupt and enable either RPE, RNE, or RHALF interrupt.
4) Read RHIR to obtain REMPTY status.
a) If REMPTY = 0, then record OBYTE, CBYTE, and POK bits and then read the FIFO.
a1) If CBYTE = 0, then skip to Step 5.
a2) If CBYTE = 1, then skip to Step 7.
b) If REMPTY=1, then skip to Step 6.
5) Repeat Step 4.
6) Wait for interrupt, skip to Step 4.
7) If POK = 0, then discard whole packet; if POK = 1, accept the packet.
8) Disable RPE, RNE, or RHALF interrupt, enable RPS interrupt and return to Step 1.
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