參數資料
型號: DS2405+
廠商: Maxim Integrated Products
文件頁數: 3/15頁
文件大?。?/td> 0K
描述: IC SWITCH ADDRESS NCH O-D TO-92
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
接口: 1 線
電源電壓: 2.8 V ~ 6 V
封裝/外殼: TO-226-3、TO-92-3 標準主體
供應商設備封裝: TO-92-3
包裝: 管件
安裝類型: 通孔
DS2405
11 of 15
Skip ROM [CCh]
The complete 1-Wire protocol for all Dallas Semiconductor iButtons contains a Skip ROM command.
Since the DS2405 contains only the 64-bit ROM with no additional data fields, the Skip ROM is not
applicable and will cause no further activity on the 1-Wire bus if executed. The DS2405 does not interfere
with other 1-Wire parts on a multidrop bus that do respond to a Skip ROM (for example, a DS2405 and
DS1994 on the same bus).
1-WIRE SIGNALING
The DS2405 requires strict protocols to ensure data integrity. The protocol consists of four types of
signaling on one line: reset sequence with Reset Pulse and Presence Pulse, write 0, write 1 and read data.
All these signals except Presence Pulse are initiated by the bus master.
The initialization sequence required to begin any communication with the DS2405 is shown in Figure 5.
A Reset Pulse followed by a Presence Pulse indicates the DS2405 is ready to send or receive data given
the correct ROM command.
The bus master transmits (TX) a Reset Pulse (tRSTL, minimum 480μs). The bus master then releases the
line and goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the 5k
Ω pullup resistor.
After detecting the rising edge on the data pin, the DS2405 waits (tPDH, 15-60μs) and then transmits the
Presence Pulse (tPDL, 60-240μs).
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 5
480
μs ≤ tRSTL < ∞*
480
μs ≤ tRSTH< ∞ (includes recovery time)
15
μs ≤ tPDH< 60μs
60
μs ≤ tPDL< 240μs
In order not to mask interrupt signaling by other devices on the 1-Wire bus, tRSTL + tR should always
be less than 960
μs.
RESISTOR
MASTER
DS2405
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