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參數(shù)資料
| 型號： | DS2406P+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 16/32頁 |
| 文件大小： | 0K |
| 描述： | IC SW ADDRESS DL W/1K MEM 6-TSOC |
| 產(chǎn)品培訓(xùn)模塊： | 1-Wire Communications Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 120 |
| 應(yīng)用： | 遙控，遙測 |
| 接口： | 1 線 |
| 電源電壓： | 2.8 V ~ 6 V |
| 封裝/外殼： | 6-LSOJ |
| 供應(yīng)商設(shè)備封裝： | 6-TSOC |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 1429 (CN2011-ZH PDF) |
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DS2406
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1-WIRE SIGNALING
The DS2406 requires strict protocols to ensure data integrity. The protocol consists of five types of
signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1, Read Data,
and Program Pulse. Except for the presence pulse the bus master initiates all these signals.
The initialization sequence required to begin any communication with the DS2406 is shown in Figure 14.
A reset pulse followed by a presence pulse indicates the DS2406 is ready to send or receive data. The bus
master transmits (TX) a reset pulse (tRSTL, minimum 480s). The bus master then releases the line and
goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the pull-up resistor. After
detecting the rising edge on the data pin, the DS2406 waits (tPDH, 15-60s) and then transmits the
presence pulse (tPDL, 60-240s).
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 14
RESISTOR
MASTER
DS2406
MASTER RX "PRESENCE PULSE"
480 s ≤ tRSTL < ∞*
480 s ≤ tRSTH < ∞ (includes recovery time)
15 s ≤ tPDH < 60 s
60 ≤ t
PDL < 240 s
MASTER TX
"RESET PULSE"
VPULLUP
VPULLUP MIN
VIH MIN
VIL MAX
0V
tRSTH
tRSTL
tPDH
tPDL
tR
* In order not to mask interrupt signaling by other devices on the 1-Wire bus, tRSTL + tR should
always be less than 960s. In a parasitically powered environment tRSTL should be limited to
maximum 5ms. Otherwise the DS2406 may perform a power-on reset.
READ/WRITE TIME SLOTS
The definitions of write and read time slots are illustrated in Figure 15. The master initiates all time slots
by driving the data line low. The falling edge of the data line synchronizes the DS2406 to the master by
triggering an internal delay circuit. During write time slots, the delay circuit determines when the DS2406
will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit
determines how long the DS2406 will hold the data line low. If the data bit is a “1”, the DS2406 will not
hold the data line low at all.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2406P/R | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Dual Addressable Switch Plus 1kbit Memory |
| DS2406P/T | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Dual Addressable Switch Plus 1kbit Memory |
| DS2406P/T&R | 制造商:Maxim Integrated Products 功能描述:IC SW DL ADDRESS W/1K MEM 6-TSOC |
| DS2406P/T&R | 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| DS2406P/TR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
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