參數(shù)資料
型號(hào)： DS2423
元件分類(lèi)： 通用總線(xiàn)功能
英文描述： 4kbit 1-Wire RAM with Counter
中文描述： 4k位1-Wire RAM，帶有計(jì)數(shù)器
文件頁(yè)數(shù)： 2/25頁(yè)
文件大?。?/td> 331K
代理商： DS2423
DS2423
2 of 25
The battery-backed memory offers a simple solution to storing and retrieving information pertaining to
the equipment where the DS2423 is installed and its frequency of use. The scratchpad is an additional
page that acts as a buffer when writing to memory. Data is first written to the scratchpad where it may be
read back for verification. A copy scratchpad command will then transfer the data to memory. This
process ensures data integrity when modifying the memory. A 64-bit registration number is factory
lasered into each DS2423 to provide a guaranteed unique identity which allows for absolute traceability
and acts as node address if multiple DS2423 are connected in parallel to form a local network. Data is
transferred serially via the 1-Wire protocol, which requires only a single data lead and a ground return.
The DS2423 1-Wire RAM with Counters can store encrypted data. The unique registration number and
the page write cycle counter(s) prevent unauthorized manipulation of data stored in a page with a write
cycle counter associated.
OVERVIEW
The block diagram in Figure 1 shows the relationships between the major control and memory sections of
the DS2423. The DS2423 has four main data components: 1) 64-bit lasered ROM, 2) 256-bit scratchpad,
3) 4096-bit SRAM, and 4) four 32-bit read-only counters. The hierarchical structure of the 1-Wire
protocol is shown in Figure 2. Each of these counters is associated with one of the 256-bit memory pages.
The four counters of the DS2423 are associated with pages 12 to 15. The contents of the counter is read
together with the memory data using a special command. The bus master must first provide one of the
six ROM Function Commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5)
Overdrive-Skip ROM or 6) Overdrive-Match ROM. Upon completion of an Overdrive ROM command
byte executed at standard speed, the device will enter Overdrive mode where all subsequent
communication occurs at a higher speed. The protocol required for these ROM function commands is
described in Figure 9. After a ROM function command is successfully executed, the memory functions
become accessible and the master may provide any one of the five memory function commands. The
protocol for these memory function commands is described in Figure 7. All data is read and written least
significant bit first.
PARASITE POWER
The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry steals power whenever
the I/O input is high. I/O will provide sufficient power as long as the specified timing and voltage
requirements are met. The advantages of parasite power are two-fold: 1) by parasiting off this input,
lithium is conserved, and 2) if the battery is exhausted for any reason, the ROM may still be read
normally.
64-BIT LASERED ROM
Each DS2423 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code.
The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits (See Figure 3).
The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates
as shown in Figure 4. The polynomial is X
8
+ X
5
+ X
4
+ 1. Additional information about the Dallas 1-
Wire Cyclic Redundancy Check is available in the
Book of DS19xx iButton
Standards
.
The shift register bits are initialized to 0. Then starting with the least significant bit of the family code,
one bit at a time is shifted in. After the 8
th
bit of the family code has been entered, then the serial number
is entered. After the 48
th
bit of the serial number has been entered, the shift register contains the CRC
value. Shifting in the 8 bits of CRC should return the shift register to all 0s.
iButton is a registered trademark of Dallas Semiconductor.
相關(guān)PDF資料
PDF描述
DS2423P 4kbit 1-Wire RAM with Counter
DS2423X 4kbit 1-Wire RAM with Counter
DS2430A The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
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